FPGA Design
An FPGA is a configurable digital circuit, not a microcontroller with a different programming language. The device contains lookup tables, flip-flops, routing switches, clock networks, block memories, DSP blocks, and I/O cells. A bitstream configures those resources into hardware.
This section builds the mental model before the syntax. You first learn programmable circuits and FPGA fabric, then the build flow, then HDL design in Verilog and VHDL, and finally simulation, timing, debugging, and validation.
Learning Objectives
By the end of this section, you should be able to:
- explain how a bitstream configures FPGA hardware;
- describe LUTs, flip-flops, routing, BRAM, DSP blocks, PLLs, and I/O cells;
- distinguish RTL hardware description from sequential software;
- build small combinational, sequential, and finite-state-machine designs;
- simulate a design with a testbench before programming a board;
- write basic pin, clock, and timing constraints;
- review timing reports and debug failing hardware systematically.
Prerequisites
You will move faster if you already know:
- Boolean logic, truth tables, multiplexers, adders, counters, and flip-flops;
- binary numbers, registers, clocks, setup time, and hold time;
- basic command-line work and version control;
- safe low-voltage lab habits and how to read a board schematic.
You do not need to be an expert in Verilog or VHDL before starting. This course treats HDL as a way to describe circuits, not as a software language to memorize.
Course Map
The order matters. A beginner can blink an LED quickly and still misunderstand the chip. Real FPGA skill comes from knowing what hardware the HDL creates, how the tools map it into the device, and how timing proves whether it can run at the requested clock frequency.
Recommended Reading Order
| Track | What it teaches | Start here |
|---|---|---|
| FPGA fundamentals | Programmable circuits, LUTs, routing, timing, clocks, memories, and toolchains | What Is an FPGA? |
| Verilog HDL | Modules, ports, combinational logic, sequential logic, FSMs, and synthesizable style | Introduction to Verilog HDL |
| VHDL | Entities, architectures, signals, types, processes, packages, and project structure | Introduction to VHDL |
| Simulation and validation | Testbenches, waveform inspection, timing failures, CDC, design review, and capstone validation | Simulation and Testbenches |
FPGA vs Firmware Thinking
Firmware runs instructions on already-built hardware. FPGA RTL describes hardware that will exist after synthesis and place-and-route.
| Habit | Firmware mindset | FPGA mindset |
|---|---|---|
| Execution | One CPU follows instructions | Many circuits operate concurrently |
| State | Variables in memory | Registers, RAMs, and FSM states |
| Timing | Usually controlled by code and interrupts | Controlled by clocks, paths, and constraints |
| Build output | Binary program | Configuration bitstream |
| Main proof | Unit tests plus target tests | Testbench, timing, constraints, and board validation |
When you write two independent continuous assignments in HDL, they usually become two pieces of hardware that react at the same time. They do not wait for each other unless you explicitly build registers, handshakes, FIFOs, or state machines.
Worked Example: One Visible Requirement
Requirement: "Blink an LED once per second."
A microcontroller solution usually configures a timer interrupt or loops with a delay. An FPGA solution builds:
- a clocked counter register;
- comparator or terminal-count logic;
- an LED output register;
- a pin constraint connecting that output to the board LED;
- a timing constraint for the input clock.
The visible result is the same. The engineering evidence is different: simulation should show counter rollover and LED toggling, timing analysis should show the clocked paths meet the target period, and the board test should confirm the correct physical pin and voltage bank.
Practical Study Loop
Use this loop for every lesson that includes HDL:
- Draw the intended hardware blocks before writing code.
- Write a small module with clear clock, reset, input, and output names.
- Simulate normal behavior and at least one edge case.
- Synthesize and read warnings.
- Apply pin and clock constraints.
- Run place-and-route and static timing analysis.
- Program hardware only after the reports make sense.
- Record what changed if hardware behavior differs from simulation.
Safety and Hardware Notes
Most examples in this section are low-voltage digital designs for education. Before connecting external hardware, check the board manual for I/O bank voltage, absolute maximum ratings, current limits, oscillator pins, configuration pins, and connector pinouts. Never connect 5 V signals to a non-5-V-tolerant FPGA input. Use level shifting, current limiting, and common ground deliberately.
Common Mistakes
- Treating HDL like C, Python, or Arduino code.
- Programming hardware before writing a testbench.
- Forgetting pin constraints or using the wrong board file.
- Ignoring timing warnings because a bitstream was generated.
- Mixing clock domains without synchronizers or FIFOs.
- Assuming a reset style is harmless without checking the target FPGA family.
- Debugging a board symptom before checking the schematic and constraints.
Summary
FPGA design is the discipline of describing, building, timing, and validating digital hardware. Start with fabric and tool flow, then learn HDL syntax as a precise way to create registers, logic, memories, interfaces, and state machines. A design is not complete just because it builds; it must simulate correctly, meet timing, use valid constraints, and behave on the real board.
Further Reading
- AMD/Xilinx: FPGA architecture and clocking user guides.
- Intel FPGA: device handbooks and timing analyzer documentation.
- Lattice Semiconductor: iCE40, ECP5, and development board documentation.
- Yosys, nextpnr, Verilator, Icarus Verilog, GHDL, and GTKWave project documentation.