Introduction to VHDL

VHDL is a hardware description language used heavily in FPGA, aerospace, industrial, defense, and long-lifecycle digital systems. It is verbose compared with Verilog, but that verbosity can make designs easier to review.

Learning Objectives

By the end of this lesson, you should be able to:

explain what VHDL is used for;
distinguish entity, architecture, signal, and process;
understand why VHDL typing feels strict;
identify synthesizable VHDL vs testbench VHDL.

First Example

library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
    port (
        a : in  std_logic;
        b : in  std_logic;
        y : out std_logic
    );
end entity;

architecture rtl of and_gate is
begin
    y <= a and b;
end architecture;

The entity describes the outside of the block. The architecture describes how the block behaves internally.

Why VHDL Feels Strict

VHDL asks you to be explicit about types. That is annoying when you start, but valuable in engineering work because many mistakes are caught early.

VHDL feature	Why it helps
strong typing	catches accidental arithmetic or width mistakes
named ports	improves review of module connections
packages	centralize reusable types, constants, and functions
explicit libraries	makes dependencies visible

Synthesizable vs Testbench Code

Code	Purpose	Goes into FPGA?
RTL architecture	describes actual hardware	yes
Testbench entity/architecture	stimulates and checks RTL	no
`wait for 10 ns`	simulation timing	no
assertions	simulation/formal checking	usually no

Mental Model

flowchart LR A["Entity"] --> B["Architecture"] B --> C["Signals"] B --> D["Processes"] B --> E["Concurrent assignments"] C --> F["Synthesis into FPGA resources"] D --> F E --> F

Worked Example: Active-Low Button

library ieee;
use ieee.std_logic_1164.all;

entity button_led is
    port (
        button_n : in  std_logic;
        led      : out std_logic
    );
end entity;

architecture rtl of button_led is
begin
    led <= not button_n;
end architecture;

This describes an inverter, not a software instruction.

Exercise

Write a VHDL entity and architecture named two_switch_led:

inputs: sw0, sw1
output: led
behavior: LED turns on only when both switches are on

Then write the Boolean expression in plain English.

Common Mistakes

Forgetting library ieee; use ieee.std_logic_1164.all;
Using std_logic_unsigned instead of numeric_std.
Treating wait for as synthesizable delay.
Confusing variables and signals.
Ignoring type conversion warnings.

Summary

VHDL is explicit, strongly typed, and excellent for reviewable FPGA designs. Learn the entity/architecture split first; then combinational logic, clocked processes, state machines, and packages become much easier.

Next: Entities, Architectures, Signals, and Types.

Mind Map

mindmap root((VHDL Basics)) Core concept Entity defines ports Architecture defines logic Strong typing Applications Applications FPGA RTL Verification Checks Design checks Library use Simulation compile Common mistakes Signal update timing Common mistakes Type mismatch