VHDL Entities, Architectures, Signals, and Types

VHDL becomes much friendlier once you separate the outside of a block from the inside. The entity is the contract. The architecture is the implementation.

Learning Objectives

You will learn to:

write entity and architecture blocks;
declare signals and vectors;
use std_logic, std_logic_vector, unsigned, and signed;
instantiate one VHDL block inside another.

Entity

entity counter8 is
    port (
        clk   : in  std_logic;
        rst   : in  std_logic;
        en    : in  std_logic;
        count : out std_logic_vector(7 downto 0)
    );
end entity;

The entity says what signals cross the module boundary. It should be easy to read without knowing the implementation.

Architecture

architecture rtl of counter8 is
    signal count_r : unsigned(7 downto 0);
begin
    count <= std_logic_vector(count_r);
end architecture;

Internal signals live before begin. Concurrent assignments and processes live after begin.

Types You Will Use Often

Type	Use
`std_logic`	one digital signal
`std_logic_vector`	bus of digital bits
`unsigned`	vector treated as an unsigned number
`signed`	vector treated as a signed number
custom `type`	states, records, clean interfaces

Use ieee.numeric_std.all for arithmetic with unsigned and signed.

Type Conversion Example

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

signal raw_count : std_logic_vector(7 downto 0);
signal count_u   : unsigned(7 downto 0);

count_u <= unsigned(raw_count);

The conversion is explicit. That extra typing prevents accidental arithmetic on nonnumeric buses.

Component Instantiation

u_and_gate : entity work.and_gate
    port map (
        a => sw0,
        b => sw1,
        y => led
    );

Named association keeps connections reviewable.

Exercise

Write an entity named nibble_swap:

input: din : in std_logic_vector(7 downto 0)
output: dout : out std_logic_vector(7 downto 0)
behavior: swap upper and lower nibbles

Expected mapping:

dout(7 downto 4) <= din(3 downto 0);
dout(3 downto 0) <= din(7 downto 4);

Common Mistakes

Writing to when the rest of the design expects downto.
Performing arithmetic on std_logic_vector instead of unsigned or signed.
Forgetting named port association.
Reusing a signal name as both input and internal register.
Hiding useful constants instead of putting them in a package.

Summary

VHDL structure is a feature: entity for boundary, architecture for implementation, explicit types for safety. Once these basics are solid, VHDL's strictness becomes a good teacher rather than an obstacle.

Next: Combinational Logic in VHDL.

Mind Map

mindmap root((VHDL Structure)) Core concept Entity boundary Architecture implementation Signals connect logic Types prevent ambiguity Applications Applications Reusable IP Top level design Design checks Checks Port modes Vector ranges Common mistakes Common mistakes downto mismatch stdlogicarith use