Combinational Logic in VHDL

Combinational logic has no memory. Its outputs depend only on current inputs. In VHDL, you can describe it with concurrent assignments or combinational processes.

Learning Objectives

By the end of this lesson, you should be able to:

• write simple concurrent assignments;
• build muxes, decoders, and Boolean functions;
• use process(all) safely;
• avoid accidental latch inference.

Concurrent Assignment

library ieee;
use ieee.std_logic_1164.all;

entity majority3 is
    port (
        a : in  std_logic;
        b : in  std_logic;
        c : in  std_logic;
        y : out std_logic
    );
end entity;

architecture rtl of majority3 is
begin
    y <= (a and b) or (a and c) or (b and c);
end architecture;

This describes combinational logic that maps naturally to LUTs.

Multiplexer

y <= b when sel = '1' else a;

For more choices:

with sel select
    y <= d0 when "00",
         d1 when "01",
         d2 when "10",
         d3 when others;

Combinational Process

Use a process when the logic is easier to read procedurally.

process(all)
begin
    y <= '0';
    if enable = '1' then
        y <= a xor b;
    end if;
end process;

The default assignment prevents latch inference.

Worked Example: 2-to-4 Decoder

process(all)
begin
    y <= "0000";
    case sel is
        when "00" => y <= "0001";
        when "01" => y <= "0010";
        when "10" => y <= "0100";
        when "11" => y <= "1000";
        when others => y <= "0000";
    end case;
end process;

Every possible input path assigns y.

Exercise

Write a 4-to-1 mux in VHDL:

• inputs: d0, d1, d2, d3
• select: sel : std_logic_vector(1 downto 0)
• output: y

Write it once using with select, and once using process(all) with a case.

Common Mistakes

• Missing a default assignment inside a combinational process.
• Forgetting when others.
• Assuming process statement order creates time delay.
• Using incomplete sensitivity lists in older VHDL styles.
• Mixing arithmetic types without conversion.

Summary

Use concurrent assignments for simple logic and process(all) for clearer decision logic. Assign every output for every input path unless you intentionally need a latch.

Next: Sequential Logic in VHDL.

Further Reading

• GHDL VHDL examples
• Vendor latch-inference warnings
• VHDL case and selected assignment references

Mind Map