Sequential Logic in VHDL

Sequential FPGA logic remembers state. In VHDL, the usual way to describe flip-flops is a clocked process using rising_edge(clk).

Learning Objectives

You will learn to:

write clocked VHDL processes;
build registers and counters;
use synchronous resets and enables;
understand signal updates inside a clocked process.

Clocked Register

process(clk)
begin
    if rising_edge(clk) then
        q <= d;
    end if;
end process;

This describes a flip-flop. On each rising clock edge, q captures d.

Counter Example

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter8 is
    port (
        clk   : in  std_logic;
        rst   : in  std_logic;
        en    : in  std_logic;
        count : out std_logic_vector(7 downto 0)
    );
end entity;

architecture rtl of counter8 is
    signal count_r : unsigned(7 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                count_r <= (others => '0');
            elsif en = '1' then
                count_r <= count_r + 1;
            end if;
        end if;
    end process;

    count <= std_logic_vector(count_r);
end architecture;

Signal Update Behavior

Inside a clocked process, signal assignments schedule updates. Think "all selected registers sample now and update together." That matches physical flip-flop behavior.

Reset Choices

Reset type	VHDL shape	Beginner guidance
synchronous	reset inside `rising_edge(clk)`	easiest to reason about in FPGA flows
asynchronous	reset checked before clock edge	useful when required, but release carefully
no reset	no reset branch	common for datapaths after system initialization is understood

Worked Example: Edge Detector

signal signal_d : std_logic;
signal rising_edge_seen : std_logic;

process(clk)
begin
    if rising_edge(clk) then
        signal_d <= signal_in;
    end if;
end process;

rising_edge_seen <= signal_in and not signal_d;

This assumes signal_in is already synchronized to clk.

Exercise

Build a 4-bit counter with:

synchronous reset;
enable input;
terminal-count output that becomes 1 when the counter equals 15.

Then explain whether terminal-count is combinational or registered in your design.

Common Mistakes

Using an unsynchronized external signal inside clocked logic.
Creating derived clocks in ordinary logic.
Resetting every datapath register by reflex.
Confusing variables and signals inside processes.
Forgetting numeric_std for arithmetic.

Summary

Clocked VHDL processes describe flip-flops. Use clear reset and enable structure, keep arithmetic types explicit, and synchronize external or cross-domain signals before using them.

Next: Finite-State Machines in VHDL.

Mind Map

mindmap root((VHDL Sequential)) Core concept risingedge clock Registers store state Reset defines start Applications Applications Counters Pipelines Timing logic Design checks Checks Reset sim Clock enable Common mistakes Common mistakes Multiple drivers Async release