Finite-State Machines in VHDL

Finite-state machines control sequences: wait, start, transmit, finish, recover. VHDL's enumerated types make FSMs readable and safe.

Learning Objectives

By the end of this lesson, you should be able to:

• draw a state diagram before coding;
• declare an enumerated state type;
• write next-state and state-register processes;
• avoid latch and unreachable-state bugs.

State Diagram First

The diagram is not paperwork. It is the design.

VHDL FSM Template

type state_t is (IDLE, LOAD, SHIFT, DONE);
signal state, next_state : state_t;

process(all)
begin
    next_state <= state;
    done <= '0';

    case state is
        when IDLE =>
            if start = '1' then
                next_state <= LOAD;
            end if;

        when LOAD =>
            next_state <= SHIFT;

        when SHIFT =>
            if bit_count_done = '1' then
                next_state <= DONE;
            end if;

        when DONE =>
            done <= '1';
            next_state <= IDLE;
    end case;
end process;

process(clk)
begin
    if rising_edge(clk) then
        if rst = '1' then
            state <= IDLE;
        else
            state <= next_state;
        end if;
    end if;
end process;

Moore vs Mealy Outputs

Beginners should start with Moore-style outputs unless there is a clear reason not to.

Worked Example: Button Debounce Control

States:

• IDLE: waiting for press;
• COUNT: input changed, count stable time;
• VALID: stable press accepted;
• WAIT_RELEASE: avoid repeated triggers.

Draw transitions before writing code. This prevents "if soup."

Exercise

Design a traffic light FSM with states:

• NS_GREEN
• NS_YELLOW
• EW_GREEN
• EW_YELLOW

Inputs are timer-done signals. Outputs drive red/yellow/green for both roads. Write the state type and transition process.

Common Mistakes

• Coding states before drawing transitions.
• Missing default assignments in next-state logic.
• Forgetting reset state.
• Making output logic depend on unsynchronized external inputs.
• Adding states with names that do not describe behavior.

Summary

VHDL FSMs become clean when you use enumerated types, defaults, a state diagram, and separate combinational next-state logic from the clocked state register.

Next: Exercise: VHDL Counter and Testbench.

Further Reading

• Vendor FSM coding templates
• GHDL simulation examples
• VHDL enumerated type references

Mind Map