What Is an FPGA and Programmable Circuit?
An FPGA is a field-programmable gate array: a digital chip whose internal hardware can be configured after manufacturing. You do not load instructions for a CPU to execute. You load a bitstream that configures logic functions, flip-flops, routing switches, clock resources, memories, and I/O behavior.
Learning Objectives
By the end of this lesson, you should be able to:
- explain programmable logic in plain language;
- distinguish FPGA, microcontroller, CPLD, and ASIC design;
- describe what a bitstream configures;
- explain why HDL describes hardware rather than software steps;
- choose whether a simple requirement is better suited to firmware or FPGA logic.
Fixed Logic, Firmware, and Programmable Logic
A fixed logic IC has permanent wiring. A 74HC08 is always a quad AND gate. A microcontroller has permanent CPU hardware, but its behavior changes because software instructions in memory change. An FPGA has fixed silicon resources whose internal connections and truth tables are configured by the bitstream.
The important word is circuit. Once configured, signals travel through physical paths. Independent logic can operate at the same time.
What the Bitstream Controls
The exact configuration format is device-specific, but conceptually the bitstream controls:
- LUT contents, which implement Boolean functions;
- flip-flop use, clock enables, and reset behavior where supported;
- routing switches between logic blocks;
- block RAM and distributed RAM configuration;
- DSP block modes for multiply, add, accumulate, and pipeline functions;
- PLL or clock-management settings;
- I/O pin functions, standards, drive strengths, and sometimes delay elements.
The bitstream is not portable across arbitrary FPGA families. A design may be portable at the RTL level, but the final implementation depends on the selected device, package, speed grade, board constraints, and toolchain.
FPGA vs Microcontroller
| Question | Microcontroller | FPGA |
|---|---|---|
| What changes behavior? | Program instructions in memory | Configured logic and routing |
| Natural execution style | Mostly sequential | Naturally concurrent |
| State storage | CPU registers and memory | Flip-flops, RAMs, FIFOs, FSM states |
| Timing model | Instruction cycles, timers, interrupts | Clock periods, path delays, setup/hold |
| Best first choice | Control, UI, networking, slow sensors | Fast I/O, parallel datapaths, exact timing |
| Beginner trap | Assuming all timing is deterministic | Assuming HDL runs line by line |
Both can blink an LED. A microcontroller usually runs a loop or timer interrupt. An FPGA builds a counter and output register.
FPGA vs CPLD vs ASIC
| Device | Good mental model | Common use |
|---|---|---|
| CPLD | Small nonvolatile programmable glue logic | address decoding, simple control, board glue |
| FPGA | Larger configurable fabric with rich resources | interfaces, accelerators, custom peripherals |
| ASIC | Custom manufactured chip | high-volume products, SoCs, CPUs, custom silicon |
CPLDs are usually smaller and simpler. FPGAs usually contain more registers, RAM, DSP, clocking, and routing capacity. ASICs can be faster, smaller, and cheaper at high volume, but they require expensive manufacturing and cannot be changed after fabrication.
HDL Describes Hardware
These two Verilog assignments describe two independent combinational networks:
assign x = a & b;
assign y = c ^ d;
The second assignment does not wait for the first. If the signals are unrelated, both pieces of hardware can change in parallel when their inputs change.
Sequential HDL creates registers only when you describe clocked storage:
always @(posedge clk) begin
q <= d;
end
That code describes a flip-flop whose output q updates on a rising clock edge. The tool does not create a software loop; it maps the behavior into FPGA resources.
Worked Example: Button-Controlled LED
Requirement: turn the LED on when a pushbutton is pressed.
The simplest logic relationship is:
assign led = button;
In hardware, the button input drives the LED output through a configured logic/routing path. The LED responds after propagation delay. No polling loop is needed.
For a real board you would also check:
- whether the button is active-high or active-low;
- whether the LED is active-high or active-low;
- whether the input needs debouncing for the application;
- whether the pin constraints match the board schematic;
- whether the I/O bank voltage is compatible with the button circuit.
Exercise
For each requirement, choose a microcontroller, FPGA, or mixed solution, then write one sentence explaining why.
| Requirement | Best first choice |
|---|---|
| Read a temperature sensor once per second and print UART text | |
| Sample 16 digital inputs at 100 MHz and detect a pattern | |
| Generate eight PWM outputs with tightly aligned edges | |
| Run a menu on a small LCD display | |
| Bridge a custom parallel camera interface to a packet FIFO |
There is not always one perfect answer. The goal is to match the tool to the timing, parallelism, and integration needs.
Common Mistakes
- Treating HDL like C or Python.
- Assuming a bitstream contains CPU instructions.
- Ignoring pin voltage, I/O standards, and board schematics.
- Starting with a large SoC project before learning LUTs, flip-flops, and timing.
- Thinking FPGA design is "faster software" instead of custom hardware.
- Forgetting that a successful build does not prove functional correctness.
Summary
An FPGA is configurable digital hardware. The bitstream sets LUT functions, routing, storage, memories, clocks, and I/O behavior. The right mental model is hardware construction, not program execution. Once you learn to think in parallel circuits, HDL becomes a precise language for creating logic.
Next: Logic Fabric, LUTs, Flip-Flops, and Routing.
Further Reading
- Yosys Manual: synthesis and technology mapping concepts.
- Vendor FPGA architecture user guides from AMD/Xilinx, Intel, and Lattice.
- Project F: FPGA tutorials for beginner-friendly RTL examples.
- Clifford Wolf, Yosys and Project IceStorm talks and documentation.