Logic Fabric, LUTs, Flip-Flops, and Routing
An FPGA is a field-programmable gate array: a digital chip whose internal hardware can be configured after manufacturing. Instead of buying a fixed logic IC for every function, you describe the hardware you want and the FPGA configures lookup tables, flip-flops, routing, memory blocks, DSP blocks, and I/O cells to behave that way.
Learning Objectives
By the end of this lesson, you should be able to:
- explain what a programmable circuit is;
- describe the role of LUTs, flip-flops, routing, I/O blocks, BRAM, DSP blocks, and clock networks;
- understand why FPGA designs are concurrent hardware, not sequential software;
- trace a simple Boolean function from truth table to LUT.
Programmable Circuits
A normal digital IC has fixed wiring. A 74HC08 is always an AND gate. A microcontroller executes instructions stored in memory. An FPGA is different: configuration bits decide what the internal logic and routing become.
The bitstream does not run like a program. It configures the chip so that signals flow through real hardware paths in parallel.
The Basic FPGA Tile
Most FPGA logic fabric is built from repeated tiles. The names differ by vendor, but the idea is consistent.
| Resource | What it does | Student mental model |
|---|---|---|
| LUT | Implements a small Boolean truth table | programmable gate |
| Flip-flop | Stores one bit on a clock edge | hardware memory bit |
| Mux | Selects one of several signals | programmable choice |
| Routing switch | Connects wires through the fabric | configurable wiring |
| Carry chain | Fast arithmetic path | dedicated adder helper |
What Is a LUT?
A lookup table, or LUT, is a tiny memory used as logic. A 4-input LUT has 16 stored bits because four inputs have 2^4 = 16 possible combinations. The input bits choose one stored output bit.
For example, a 2-input XOR truth table is:
| A | B | A XOR B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The LUT stores 0, 1, 1, 0. When A and B change, the LUT output changes after a small propagation delay.
LUTs Are Not Slow Software Tables
The word “lookup” can mislead beginners. A LUT is not a CPU reading an array. It is hardware memory wired so the address lines are the logic inputs and the selected memory bit is the output. The selection happens electrically.
Flip-Flops Make State
Combinational logic only reacts to current inputs. Sequential logic remembers previous events using flip-flops.
title "Illustrative flip-flop sampling"
time start=0 end=8 unit=ns divisions=8
CLK: square label="clock" low=0 high=1 duty=50 cycles=4 unit=logic color=#2563eb
D: step label="D input changes before edge" low=0 high=1 at=2.4 unit=logic color=#dc2626
Q: step label="Q updates at next active edge" low=0 high=1 at=4 unit=logic color=#16a34a
marker EDGE at=4 label="sampling edge"
This waveform is explanatory. Real devices have setup time, hold time, clock-to-Q delay, jitter, and routing delay.
The Routing Fabric
The LUTs and flip-flops are useful only if signals can travel between them. Routing resources are programmable wires and switches spread across the FPGA. Place-and-route tools choose where each logic element sits and which routing tracks connect it.
This is why two designs with the same HDL can have different timing after implementation: the physical route matters.
Dedicated Blocks
Modern FPGAs include more than LUTs:
- Block RAM (BRAM) for FIFOs, frame buffers, tables, and packet queues.
- DSP slices for fast multiply-accumulate operations.
- PLL/MMCM clocking blocks for clock generation and phase alignment.
- SerDes/transceivers on larger devices for high-speed serial links.
- I/O blocks that handle standards, drive strength, input registers, and sometimes delay tuning.
Using these dedicated blocks is normal. Trying to build everything from LUTs wastes area and hurts timing.
Worked Example: A 3-Input Majority Function
The output is 1 when at least two of A, B, and C are 1.
| A | B | C | Y |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |
Boolean form:
Y = (A & B) | (A & C) | (B & C)
A 3-input LUT can implement this directly by storing the eight output bits.
Common Mistakes
- Thinking the FPGA “executes” HDL line by line.
- Forgetting that routing delay is part of the design.
- Treating LUT count as the only resource that matters.
- Ignoring dedicated BRAM and DSP blocks.
- Assuming an unconstrained design is a verified design.
Summary
An FPGA configures hardware after manufacturing. LUTs implement Boolean functions, flip-flops store state, routing connects resources, and dedicated blocks handle common heavy tasks. The big shift from software is concurrency: many pieces of hardware operate at the same time.
Next: Open-Source FPGA Toolchains: Yosys, nextpnr, APIO.
Further Reading
- AMD/Xilinx: 7 Series FPGAs Configurable Logic Block User Guide
- Intel: Intel FPGA Architecture and Device Families
- Lattice: FPGA family handbooks and getting-started guides
- Yosys Manual: synthesis and technology mapping concepts