Introduction to Verilog HDL

Verilog is a hardware description language. It can look like C at first glance, but it does not describe a program that runs on an FPGA. It describes circuits that synthesis tools build from FPGA resources.

Learning Objectives

By the end of this lesson, you should be able to:

explain what HDL means;
identify synthesizable vs testbench-only Verilog;
understand modules, ports, nets, and registers at a high level;
avoid the "Verilog is software" beginner mistake.

What Verilog Describes

This tiny module describes a two-input AND gate:

module and_gate (
    input  wire a,
    input  wire b,
    output wire y
);
    assign y = a & b;
endmodule

There is no loop here. There is no CPU instruction. The output y is driven by combinational logic created from a and b.

Synthesizable Code vs Testbench Code

Code type	Purpose	Goes into FPGA?
Synthesizable RTL	describes real hardware	yes
Testbench	stimulates and checks RTL in simulation	no
Assertions/checkers	catch mistakes during simulation/formal checks	usually no, unless supported intentionally

Beginner rule: if the code says "wait 10 ns" or prints text, it is probably testbench code, not hardware.

Important Verilog Words

Word	Meaning
`module`	reusable hardware block
`input`, `output`	external ports
`wire`	connection driven by continuous logic or another module
`reg` / `logic`	signal assigned inside procedural blocks
`assign`	continuous combinational assignment
`always`	procedural block used to describe combinational or clocked hardware

Modern SystemVerilog often uses logic instead of old Verilog's reg for internally assigned signals. Many FPGA examples still use wire and reg, so students should recognize both.

The FPGA Mental Model

flowchart LR A["Verilog module"] --> B["Synthesis"] B --> C["LUTs"] B --> D["Flip-flops"] B --> E["RAM / DSP blocks"] B --> F["Routing"]

Your code is a description. The synthesis tool decides which LUTs, flip-flops, and routing resources implement it.

Worked Example: Active-Low Button

Many boards wire push buttons as active-low. Pressed means 0, released means 1.

module button_led (
    input  wire button_n,
    output wire led
);
    assign led = ~button_n;
endmodule

This creates one inverter between the physical input and output.

Exercise

Write a Verilog module named two_switch_led:

inputs: sw0, sw1
output: led
behavior: LED turns on only when both switches are on

Then draw the logic gate you expect synthesis to create.

Common Mistakes

Thinking each Verilog line executes one after another.
Using delays such as #10 in synthesizable design code.
Forgetting that signal width matters.
Mixing testbench code into the design module.
Copying SystemVerilog examples into tools configured for older Verilog.

Summary

Verilog describes hardware blocks. Use it to describe combinational logic, registers, state machines, memories, and interfaces. Simulators execute the description for checking; synthesis tools turn the synthesizable subset into FPGA hardware.

Next: Modules, Ports, Wires, and Regs.

Mind Map

mindmap root((Verilog HDL)) Core concept Modules describe hardware assign for combinational always blocks need intent Applications Applications RTL design Testbenches Checks Design checks Synthesis warnings Simulation result Common mistakes Thinking sequential text Common mistakes Latch inference