Verilog Simulation: Verilator, Icarus Verilog, and GTKWave

Simulation lets you catch mistakes before hardware. For Verilog, students commonly use Verilator for fast linting/simulation and Icarus Verilog for lightweight event-driven simulation.

Learning Objectives

By the end of this lesson, you should be able to:

• choose a simulator for a beginner project;
• run basic Verilator and Icarus Verilog commands;
• generate VCD waveforms;
• inspect signals in GTKWave;
• understand why passing simulation is necessary but not sufficient.

Verilator

Verilator is excellent for linting and fast simulation. A tiny smoke test can be built like this:

verilator --binary -j 0 -Wall top_tb.sv
./obj_dir/Vtop_tb

--binary asks Verilator to build a runnable simulation executable. -Wall enables stronger warnings. -j 0 lets the build use available CPU threads.

Icarus Verilog

Icarus Verilog is simple and friendly for classic Verilog testbenches.

iverilog -g2012 -o sim.out top.v top_tb.v
vvp sim.out

To produce a waveform, the testbench should include:

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, top_tb);
end

Then view it:

gtkwave wave.vcd

What to Put in a Testbench

A waveform-only testbench is better than nothing, but a self-checking testbench is stronger because it fails automatically.

Worked Example: Counter Check

Checklist:

1. reset the counter;
2. release reset on a known edge;
3. enable counting;
4. check count after several cycles;
5. test enable low;
6. test wrap-around.

Do not only check the happy path.

Exercise

Use the Verilog 4-bit counter from the Verilog lessons and create a testbench that:

• generates a 100 MHz clock;
• holds reset high for three cycles;
• checks that count increments only when enable is high;
• writes counter.vcd;
• opens the waveform in GTKWave.

Common Mistakes

• Looking at waveforms manually but not writing checks.
• Forgetting $finish.
• Sampling outputs on the wrong clock edge.
• Ignoring simulator warnings.
• Assuming simulation checks timing constraints.

Summary

Use Verilator for strong warnings and fast simulation, Icarus Verilog for simple event-driven Verilog testbenches, and GTKWave to inspect timing visually. Simulation catches logic mistakes; synthesis and timing analysis still need their own checks.

Next: GHDL and VHDL Simulation.

Further Reading

• Verilator examples
• Icarus Verilog documentation
• GTKWave manual

Mind Map