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GHDL and VHDL Simulation

GHDL is the most common open-source VHDL simulator for students. It follows the VHDL build model: analyze files, elaborate a top-level design, then run the simulation.

Learning Objectives

You will learn to:

  • analyze VHDL source files with GHDL;
  • elaborate and run a testbench;
  • generate VCD waveforms;
  • use assertions to make tests self-checking.

Basic GHDL Flow

ghdl -a counter4.vhd
ghdl -a counter4_tb.vhd
ghdl -e counter4_tb
ghdl -r counter4_tb

The usual meanings are:

Command Meaning
ghdl -a analyze/compile source files
ghdl -e elaborate the selected top entity
ghdl -r run the elaborated design

Some GHDL backends allow -r to elaborate automatically, but beginners should learn the three-step model.

Dumping a Waveform

ghdl -r counter4_tb --vcd=counter4.vcd
gtkwave counter4.vcd

Waveforms help you see timing relationships, but assertions should still decide pass/fail.

Self-Checking Testbench Habit

assert count = "0001"
    report "counter did not increment"
    severity error;

If the design is wrong, the simulator should complain without relying on your eyes.

Larger Projects

For multiple files, analyze packages first:

ghdl -a rtl/common_pkg.vhd
ghdl -a rtl/uart_tx.vhd
ghdl -a tb/uart_tx_tb.vhd
ghdl -e uart_tx_tb
ghdl -r uart_tx_tb --vcd=uart_tx.vcd

VHDL compile order matters because a file can depend on packages, entities, or architectures analyzed earlier.

Exercise

Run the VHDL counter exercise using GHDL:

  1. intentionally break the increment line;
  2. confirm the assertion fails;
  3. fix the design;
  4. regenerate the VCD;
  5. inspect reset, enable, and count in GTKWave.

Common Mistakes

  • Analyzing files in the wrong order.
  • Running the design entity instead of the testbench entity.
  • Forgetting to stop the testbench.
  • Treating a waveform as proof without assertions.
  • Mixing generated files with source files.

Summary

GHDL gives VHDL students a transparent simulation workflow: analyze, elaborate, run, and inspect waveforms. Use assertions so your testbench becomes a checking tool, not just a waveform generator.

Next: Exercise: Find and Fix a Timing Failure.

Further Reading

  • GHDL quick start
  • GHDL invoking guide
  • GTKWave manual

Mind Map

mindmap root((GHDL)) Core concept Analyze files Elaborate top Run testbench VCD optional Applications Applications VHDL regression CI checks Design checks Checks Compile order assert failures Common mistakes Common mistakes Missing package compile Entity name mismatch