Pin Planning and Constraints

HDL describes internal behavior. Constraints connect that behavior to the real board and tell the tools what timing must be met. Without constraints, an FPGA design is incomplete.

Learning Objectives

By the end of this lesson, you should be able to:

• explain why pin constraints and timing constraints are part of the design;
• map top-level HDL ports to physical FPGA pins;
• choose I/O standards carefully;
• define a basic clock constraint;
• recognize dangerous constraint mistakes.

Two Major Constraint Types

Both matter. A perfect HDL module connected to the wrong pin is still broken. A design with no clock constraint may pass implementation without meeting the real board frequency.

Top-Level Ports Must Match the Board

Example top module:

module top (
    input  wire clk_100mhz,
    input  wire btn0,
    output wire led0
);
    assign led0 = btn0;
endmodule

The FPGA tool needs to know which package pins correspond to clk_100mhz, btn0, and led0.

Example XDC-Style Constraints

Exact names and pin numbers depend on the board.

set_property PACKAGE_PIN E3 [get_ports clk_100mhz]
set_property IOSTANDARD LVCMOS33 [get_ports clk_100mhz]
create_clock -name sys_clk -period 10.000 [get_ports clk_100mhz]

set_property PACKAGE_PIN D9 [get_ports btn0]
set_property IOSTANDARD LVCMOS33 [get_ports btn0]

set_property PACKAGE_PIN H17 [get_ports led0]
set_property IOSTANDARD LVCMOS33 [get_ports led0]

Why I/O Standards Matter

The FPGA pin is part of an I/O bank powered by a board voltage. Choosing the wrong standard can cause unreliable behavior or hardware damage.

Always check the board schematic and FPGA bank voltage before choosing an I/O standard.

Clock Constraints

Timing tools need the clock period. A 100 MHz clock has a 10 ns period:

period = 1 / frequency = 1 / 100 MHz = 10 ns

If the real board oscillator is 50 MHz, the period is 20 ns. Use the actual clock.

Worked Example: LED Blink Constraints

Requirement:

• board clock: 100 MHz;
• one button input;
• one LED output;
• all signals in a 3.3 V I/O bank.

Minimum constraint checklist:

1. clock pin location;
2. clock I/O standard;
3. clock period;
4. button pin location and I/O standard;
5. LED pin location and I/O standard.

If any one is missing, the build may still produce a bitstream, but it is not a trustworthy hardware design.

Common Mistakes

• Copying constraints from a different board.
• Forgetting to constrain the clock.
• Using the wrong I/O voltage standard.
• Renaming HDL ports without updating constraints.
• Ignoring critical warnings about unconstrained pins or clocks.

Summary

Constraints bind HDL to real hardware. Pin constraints define physical connections. I/O standards define electrical behavior. Clock constraints define timing requirements. Treat constraints as design source, review them like code, and keep them under version control.

Next: Static Timing Analysis.

Further Reading

• AMD Vivado constraints guide
• Intel Quartus timing analyzer documentation
• Lattice constraints documentation
• Your FPGA board schematic and user manual

Mind Map