Pin Planning and Constraints

HDL describes logic inside the FPGA. Constraints connect that logic to the board and tell the implementation tools what electrical and timing rules the design must obey. A bitstream built from unconstrained HDL is not a complete hardware design.

Learning Objectives

By the end of this lesson, you should be able to:

• map top-level HDL ports to physical package pins;
• choose I/O standards from the board schematic and I/O-bank voltage;
• define primary clock constraints from real oscillator frequencies;
• review unconstrained pins, clocks, and paths before programming hardware;
• recognize constraint mistakes that can damage hardware or create intermittent failures.

Constraints Are Design Source

Constraints are not optional tool settings. They are source files that express board-level requirements.

Keep constraints under version control with the HDL. Review them during code review because a one-line pin mistake can connect a push button to an LED output, short two outputs together, or apply the wrong voltage standard to an I/O bank.

Match Top-Level Ports to the Board

A top-level HDL port name must match the name used in the constraint file.

module top (
    input  wire clk_100mhz,
    input  wire btn0_n,
    output wire led0
);
    assign led0 = ~btn0_n;
endmodule

The board schematic and user manual decide the physical pins. The HDL does not know that clk_100mhz is connected to package pin E3 or that btn0_n is active-low.

Example XDC-Style Constraints

Exact syntax and pin names vary by vendor. This example uses an XDC-style format:

set_property PACKAGE_PIN E3 [get_ports clk_100mhz]
set_property IOSTANDARD LVCMOS33 [get_ports clk_100mhz]
create_clock -name sys_clk -period 10.000 [get_ports clk_100mhz]

set_property PACKAGE_PIN D9 [get_ports btn0_n]
set_property IOSTANDARD LVCMOS33 [get_ports btn0_n]
set_property PULLUP true [get_ports btn0_n]

set_property PACKAGE_PIN H17 [get_ports led0]
set_property IOSTANDARD LVCMOS33 [get_ports led0]
set_property DRIVE 8 [get_ports led0]
set_property SLEW SLOW [get_ports led0]

The names clk_100mhz, btn0_n, and led0 must match the top-level module exactly. If the HDL port is renamed, update the constraints in the same commit.

I/O Standards and Bank Voltage

FPGA I/O pins are grouped into banks. Each bank is powered by a board rail such as 3.3 V, 2.5 V, or 1.8 V. The selected I/O standard must be compatible with that rail and with the external device.

Never guess an I/O standard from a tutorial. Check the board schematic, FPGA package pins, I/O-bank voltage, and external device absolute maximum ratings.

Clock Period Formula

Timing constraints use period, not frequency.

T = 1 / f

For common FPGA clocks:

If a board oscillator is 100 MHz, the primary clock constraint is:

create_clock -name sys_clk -period 10.000 [get_ports clk_100mhz]

If a PLL creates another clock, constrain the generated clock using the vendor-recommended method. Do not rely on the tool to infer every generated clock correctly.

Worked Example: LED Blink Constraint Review

Requirement:

• board oscillator: 100 MHz;
• active-low push button in a 3.3 V bank;
• LED driven from a 3.3 V bank;
• no external high-speed interface.

Minimum review:

1. Confirm the oscillator pin and period: 100 MHz means 10 ns.
2. Confirm the button package pin and active-low naming.
3. Confirm the LED package pin, drive current, and bank voltage.
4. Check the implementation report for unconstrained ports and clocks.
5. Treat any critical warning about pin, clock, or timing constraints as a build failure until reviewed.

Constraint Review Checklist

Before programming a board:

• every top-level port has an intentional pin assignment or is deliberately removed;
• every I/O port has a compatible I/O standard;
• bank voltages match the board schematic;
• primary clocks have correct periods;
• generated clocks are present where the design uses PLLs or clock dividers;
• asynchronous inputs are synchronized in RTL, not hidden with timing exceptions;
• false-path and multicycle exceptions have written design justification;
• timing reports show no unconstrained internal paths that matter.

Common Mistakes

• Copying a constraint file from a different board revision.
• Using LVCMOS33 because it is familiar while the bank is powered at 1.8 V.
• Forgetting that active-low buttons and resets should be named clearly, such as btn0_n.
• Renaming HDL ports without updating get_ports constraints.
• Leaving the clock unconstrained and trusting a successful bitstream build.
• Adding false paths to silence warnings instead of understanding the crossing.

Summary

Pin planning turns HDL ports into real board connections. I/O standards define electrical compatibility. Clock constraints define the timing target. A reliable FPGA project treats constraints as reviewed design source, not as a final build setting.

Next: Static Timing Analysis.

Further Reading

• AMD Vivado Design Suite User Guide: Using Constraints
• Intel Quartus Prime Timing Analyzer documentation
• Lattice Diamond and Radiant constraint documentation
• Your FPGA board schematic, user manual, and FPGA package pinout

Mind Map