Static Timing Analysis

Static timing analysis, usually called STA, checks whether every constrained timing path can meet the clock rules after synthesis, placement, and routing. It is static because the tool analyzes delays mathematically instead of simulating every possible input pattern.

Functional simulation asks, "Does the logic do the right thing?" STA asks, "Can the implemented hardware do it before the next clock edge?"

Learning Objectives

You will learn to:

• explain launch registers, capture registers, setup time, and hold time;
• calculate simple setup slack from period and path delay;
• interpret positive, zero, and negative slack;
• identify critical paths and common timing-closure fixes;
• avoid unsafe timing exceptions.

The Register-to-Register Path

Most synchronous timing checks start at one flip-flop and end at another flip-flop.

The source register launches data on an active clock edge. The destination register captures that data on a later active clock edge. LUT delay, carry-chain delay, net delay, clock skew, uncertainty, and setup/hold requirements decide whether the path is safe.

Setup Timing

Setup time is the minimum time data must be stable before the destination clock edge.

For a simple same-clock path:

setup slack = Tclk - Tcq - Tlogic - Troute - Tsetup - Tuncertainty + Tskew

Where:

• Tclk is the clock period in ns;
• Tcq is launch flip-flop clock-to-Q delay;
• Tlogic is combinational logic delay;
• Troute is interconnect delay;
• Tsetup is the destination flip-flop setup requirement;
• Tuncertainty covers jitter and tool margin;
• Tskew is useful or harmful clock arrival difference, depending on sign.

Positive setup slack means the data arrives early enough. Negative setup slack means the destination may capture the old value or an unstable value.

Hold Timing

Hold time is the minimum time data must remain stable after the destination clock edge. A hold problem is often a path that is too fast or a clock-skew problem.

For a simple same-clock path:

hold slack = Tcq_min + Tlogic_min + Troute_min - Thold - Tskew - Tuncertainty

Hold failures cannot be fixed by lowering the clock frequency. The clock period is not the limiting term. FPGA tools usually fix hold issues by adding routing delay or changing placement, but bad clocking and unsafe CDC can still create real failures.

title "Illustrative setup and hold window"
time start=0 end=10 unit=ns divisions=10

CLK: square label="destination clock" low=0 high=1 duty=50 cycles=1 unit=logic color=#2563eb
D_OK: step label="data stable before edge" low=0 high=1 at=3 unit=logic color=#16a34a
D_LATE: step label="late data violates setup" low=0 high=1 at=4.8 unit=logic color=#dc2626

marker SETUP at=4.5 label="setup"
marker EDGE at=5 label="capture"
marker HOLD at=5.5 label="hold"

This waveform is explanatory. Real setup and hold windows are device-specific and come from the timing model.

Slack and Critical Paths

Slack is margin:

slack = required time - arrival time

The critical path is the constrained path with the worst slack. It limits the achievable clock frequency for that build.

Worked Example: 100 MHz Failure

A design targets 100 MHz, so:

Tclk = 1 / 100 MHz = 10 ns

Suppose the timing report shows:

required time:       10.000 ns
data arrival time:   12.000 ns
setup slack:         -2.000 ns

The design does not safely run at 100 MHz. A rough maximum frequency estimate from this path is:

Fmax approx = 1 / 12 ns = 83.3 MHz

This estimate is useful for intuition, but the real fix should come from the timing report.

Timing-Closure Fixes

Use design fixes before tool tricks:

• pipeline long arithmetic, filters, or address-generation paths;
• register module boundaries when wide combinational logic crosses them;
• use FPGA carry chains, DSP blocks, or BRAM instead of LUT-heavy structures;
• reduce fanout on enable, reset, and control signals;
• avoid fabric-generated clocks and clock gating;
• constrain generated clocks correctly;
• floorplan only when RTL and constraints are already clean.

Timing Exceptions Need Evidence

False paths and multicycle paths are powerful and dangerous. A false path says the path does not need timing analysis. A multicycle path says the destination is allowed more than one clock cycle.

Use exceptions only when the architecture proves they are valid. Document the reason next to the constraint. Do not use exceptions to hide timing failures caused by ordinary synchronous logic.

Common Mistakes

• Assuming functional simulation proves timing.
• Ignoring negative slack because one board "seems to work."
• Reading only setup slack and never checking hold slack.
• Forgetting generated clocks from PLLs or clock dividers.
• Marking CDC paths false without adding synchronizers, handshakes, or FIFOs.
• Chasing placement changes while the RTL still has too much logic between registers.

Summary

Static timing analysis proves that implemented register-to-register paths meet clock requirements. Setup checks catch late data. Hold checks catch data changing too soon. Slack is the timing margin, and the worst slack path guides timing closure. A passing simulation with failing STA is not a reliable FPGA design.

Next: Clocks, Resets, and PLLs.

Further Reading

• AMD Vivado Design Suite User Guide: Design Analysis and Closure Techniques
• Intel Quartus Prime Timing Analyzer Cookbook
• Synopsys Design Constraints timing concepts
• FPGA vendor methodology guides for synchronous design

Mind Map