Design Flow: Synthesis, Place-and-Route, and Bitstream
Hardware description languages describe circuits. The FPGA tool flow transforms that description into a configured chip through simulation, synthesis, place-and-route, timing analysis, and bitstream generation.
Learning Objectives
After this lesson, you will be able to:
- explain where HDL fits in the FPGA build flow;
- distinguish synthesis, place-and-route, and bitstream generation;
- follow the FPGA flow from source files to bitstream;
- identify where simulation, constraints, timing analysis, and hardware validation happen.
HDL Is a Hardware Description
This assignment:
assign y = (a & b) | c;
does not mean “the CPU should compute a & b, then OR with c.” It means the synthesized hardware should contain combinational logic whose output is continuously driven by that expression.
The same idea in VHDL:
y <= (a and b) or c;
Both describe a circuit.
Verilog and VHDL in the Flow
| Topic | Verilog/SystemVerilog style | VHDL style |
|---|---|---|
| Syntax feel | compact, C-like | explicit, strongly typed |
| Common in | ASIC and FPGA design, many examples online | aerospace, defense, Europe, formal/typed flows |
| Beginner advantage | quick to write | fewer accidental type assumptions |
| Beginner risk | easy to write ambiguous code | more syntax before first success |
You do not need to treat this as a religion. Learn the hardware concepts; then syntax becomes a translation problem. This fundamentals track explains the tool flow; the Verilog and VHDL tracks teach the languages separately.
The FPGA Flow
Simulation appears early because it is cheaper to catch functional errors before synthesis. Static timing appears after implementation because physical delay depends on placement and routing.
RTL: Register Transfer Level
Most beginner FPGA design is RTL. You describe:
- registers that update on clock edges;
- combinational logic between registers;
- control state machines;
- memories, counters, interfaces, and datapaths.
The synthesis tool maps that RTL to FPGA resources.
Constraints Are Part of the Design
An FPGA tool cannot guess everything. You must tell it:
- which clock frequency the design must meet;
- which top-level signal connects to which physical pin;
- what I/O voltage standard each pin uses;
- any special timing exception that is real and justified.
An unconstrained design may build and still be wrong.
Worked Example: One LED Register
Requirement: pressing a button should toggle an LED once per clean button event. The flow is:
- write RTL for synchronizing the button and toggling a register;
- simulate button edges and verify LED toggles;
- constrain the board clock and LED/button pins;
- synthesize and implement;
- confirm timing passes;
- program the board and test with the actual button.
If you skip simulation, you may not notice bounce, missing synchronization, or a wrong edge detector until hardware.
Common Mistakes
- Writing HDL like sequential C code.
- Believing successful synthesis means correct behavior.
- Forgetting pin constraints or I/O standards.
- Ignoring warnings because “the bitstream was generated.”
- Testing only on hardware and never writing a testbench.
Summary
HDL describes hardware. The FPGA flow turns HDL into configured fabric through simulation, synthesis, constraints, place-and-route, timing analysis, bitstream generation, and board validation. Verilog and VHDL differ in syntax and style, but both require the same hardware thinking.
Next: Pin Planning and Constraints.
Further Reading
- IEEE 1800 SystemVerilog standard overview
- IEEE 1076 VHDL standard overview
- Verilator documentation
- GHDL documentation
- Vendor FPGA design flow user guides