EMC, ESD, Thermal, and Mechanical Design
A PCB must survive more than schematic logic. It must fit the enclosure, reject interference, handle electrostatic discharge, move heat, tolerate cables, and remain serviceable. These constraints should be designed in early, not patched after failure.
Learning Objectives
By the end of this lesson, you should be able to plan EMC and ESD paths, estimate thermal rise, place hot and exposed parts, review connector mechanics, and check enclosure and mounting constraints before release.
EMC Starts With Current Loops
Radiated emissions increase with fast current, large loop area, and poor return paths. Reduce loop area by keeping signal and return close, using solid planes, placing decoupling capacitors correctly, and keeping switching regulator hot loops compact.
ESD Path Planning
ESD current should be diverted at the entry point. Place TVS devices close to connectors with a short, low-inductance path to chassis or the intended return. Do not route ESD current through the center of the logic ground plane if a better chassis path exists.
Check:
- exposed connector pins;
- buttons, displays, shields, and metalwork;
- cable shields;
- creepage and clearance for higher voltages;
- TVS capacitance on high-speed lines.
Thermal Design
Power loss becomes heat:
[
P=VI
]
For a linear regulator:
[
P_{LOSS}=(V_{IN}-V_{OUT})I_{OUT}
]
Approximate temperature rise:
[
\Delta T=P\theta_{JA}
]
where (\theta_{JA}) is junction-to-ambient thermal resistance in degC/W. Copper area, airflow, vias, enclosure temperature, and neighboring heat sources all affect the real result.
Mechanical Constraints
Mechanical design includes:
- board outline and keepouts;
- mounting holes and screw head clearance;
- connector positions and mating direction;
- enclosure height and cable bend radius;
- test-point access after assembly;
- labels visible in the final product.
Export board outlines and connector positions for mechanical review before layout is complete.
Reliability Details
Derate components for voltage, current, power, and temperature. Avoid placing brittle ceramic capacitors near board edges, screw holes, or flex zones. Provide strain relief for heavy cables. Keep tall parts away from covers and vibration-sensitive locations.
Practical Review Checklist
- Identify all external entry points for ESD and surge.
- Keep TVS paths short and direct.
- Check hot-loop area in switching supplies.
- Estimate worst-case regulator and MOSFET heating.
- Verify enclosure, mounting, connector, and cable clearances.
- Confirm labels and test points are usable after assembly.
Common Mistakes
- Adding TVS devices far from the connector.
- Routing shield or ESD current through sensitive logic ground.
- Trusting package power rating without copper and ambient checks.
- Placing connectors without cable bend clearance.
- Discovering enclosure interference after boards are fabricated.
Summary
EMC, ESD, thermal, and mechanical design are connected. Current loops create emissions, ESD needs a planned path, heat needs copper and airflow, and the board must physically fit and survive real handling.
Further Reading
- Henry Ott, "Electromagnetic Compatibility Engineering."
- IEC 61000-4-2 ESD immunity test concepts.
- Texas Instruments, "Thermal Design by Insight, Not Hindsight."