Routing Fundamentals

Routing turns the schematic into copper. A routed trace is not an ideal line: it has resistance, inductance, capacitance, return current, coupling, and manufacturing limits. Good routing is electrically intentional and easy to review.

Learning Objectives

By the end of this lesson, you should be able to choose trace widths, respect spacing rules, use vias intentionally, route critical signals first, preserve return paths, and review routing for manufacturing and electrical risk.

Routing Priority

Route constrained signals first:

power entry and high-current paths;
clocks, crystals, and high-speed interfaces;
analog inputs and references;
differential pairs and impedance-controlled traces;
remaining low-speed digital signals.

Leave enough room for return current, decoupling loops, and test points.

Trace Width and Resistance

Trace resistance follows:

[
R = \rho \frac{L}{A}
]

where (L) is trace length and (A) is copper cross-sectional area. Wider traces lower resistance and temperature rise. For high current, use a trace-width calculator or fabricator guidance and include temperature-rise assumptions.

Voltage drop is:

[
V_{DROP} = I R
]

This matters for motors, LEDs, radios, and precision analog supplies.

Return Paths

Every signal has a return current. Keep the outgoing trace close to its return plane or return trace. Avoid routing across a split plane because the return current must detour around the gap.

flowchart LR Driver --> Trace[Signal trace] Trace --> Load Load --> Return[Nearest return path] Return --> Driver

The signal trace and return path form the loop area that radiates and receives noise.

Vias

Vias add inductance, resistance, and manufacturing complexity, but they are necessary. Use them deliberately:

multiple vias for high current and thermal paths;
stitching vias near layer changes for high-speed return current;
tented or filled vias only when the process requires it;
avoid vias in pads unless the assembly process supports them.

Differential Pairs

For USB, Ethernet, LVDS, and other differential signals:

confirm impedance target from the interface standard;
route pair members together;
keep length mismatch within the interface requirement;
avoid unnecessary stubs;
maintain reference plane continuity;
place common-mode chokes or ESD parts according to vendor guidance.

Common Mistakes

Routing low-priority signals first and blocking critical paths.
Using the same narrow width for logic and high-current loads.
Crossing plane splits with clocks or fast edges.
Adding too many vias to sensitive analog inputs.
Forgetting clearance for high voltage or dirty environments.

Summary

Routing is controlled copper geometry. Good routing checks width, spacing, current, voltage drop, return paths, vias, impedance, and reviewability.

Mind Map

mindmap root((Routing)) Core concept Copper has parasitics Return path matters Critical routes first Formulas R=rho*L/A Vdrop=I*R P=I^2*R Loop area drives EMI Applications Power traces Clocks Differential pairs Analog inputs Design rules Route constraints first Avoid plane gaps Use vias intentionally Follow spacing rules Practical checks Trace width Via count Length mismatch Clearance Common mistakes Thin high current trace Broken return Stub left behind Late critical routing