Layer Stackup and Materials

The layer stackup defines the physical structure of a PCB: copper layers, dielectric thickness, material type, copper weight, solder mask, and surface finish. It controls routing density, return paths, impedance, heat spreading, cost, and manufacturability.

Learning Objectives

By the end of this lesson, you should be able to choose a layer count, explain why reference planes matter, identify material parameters, estimate impedance drivers, and communicate a stackup to a PCB fabricator.

What a Stackup Specifies

A stackup should include:

number of copper layers;
layer order and purpose;
dielectric material and thickness;
copper weight or finished copper thickness;
controlled-impedance targets;
prepreg/core construction;
solder mask and surface finish;
minimum trace/space and drill limits.

Do not assume every fabricator uses the same "standard four-layer board." Ask for their preferred stackup early.

Common Layer Counts

Layer count	Typical use	Notes
2	simple low-speed boards	harder return paths, low cost
4	most embedded boards	signal, plane, plane, signal is common
6	denser boards, mixed signal	more routing and plane options
8+	high-speed, dense, controlled impedance	higher cost and review effort

A four-layer board often costs more than a two-layer board, but can save debugging time by providing better ground and power planes.

Reference Planes and Return Current

Every signal current returns to its source. At high frequency, return current follows the nearest reference plane under the signal trace. If the plane is split or interrupted, the return path detours and creates EMI, crosstalk, and signal integrity problems.

flowchart LR Driver[Driver] --> Trace[Signal trace] Trace --> Receiver[Receiver] Receiver --> Plane[Return current in reference plane] Plane --> Driver

The signal path and return path are a loop. A good stackup keeps that loop small.

Material Parameters

Important material properties:

(D_k): dielectric constant, affects impedance and propagation delay.
(D_f): dissipation factor, affects high-frequency loss.
(T_g): glass transition temperature.
CTE: thermal expansion behavior.
copper roughness: affects high-speed loss.

FR-4 is not one exact material. High-speed, high-temperature, or high-reliability products may need a specified laminate family.

Impedance Basics

Controlled impedance depends on trace width, copper thickness, dielectric thickness, solder mask, and (D_k). Exact values require a field solver or fabricator calculator, but the design rule is simple: impedance is a geometry-plus-material property, not a schematic symbol.

Typical targets:

USB differential pair: 90 ohm differential.
Ethernet differential pair: 100 ohm differential.
RF single-ended paths: often 50 ohm.

Copper Weight and Current

Copper thickness affects resistance, current heating, and etching precision. One ounce copper is about 35 um thick before processing. Heavier copper can carry more current but makes fine features harder.

Resistance is:

[
R = \rho \frac{L}{A}
]

where (\rho) is copper resistivity, (L) is length, and (A) is cross-sectional area.

Practical Four-Layer Starting Point

A common embedded stackup:

Layer	Purpose
L1	components and critical signals
L2	solid ground plane
L3	power plane or power plus signals
L4	slower signals and components

Keep L2 as continuous ground whenever possible. Avoid routing critical signals over plane gaps.

Common Mistakes

Selecting two layers for a noisy mixed-signal board only to save prototype cost.
Splitting the ground plane without a return-current plan.
Routing controlled-impedance signals before the stackup is confirmed.
Ignoring copper thickness in current and voltage-drop estimates.
Failing to document impedance and material requirements in fabrication notes.

Summary

Stackup is an electrical and manufacturing decision. Choose layers, materials, copper, and planes early, then confirm them with the fabricator before final routing.

Mind Map

mindmap root((PCB stackup)) Core concept Physical board structure Planes guide returns Materials set impedance Formulas R=rho*L/A Delay depends on Dk Impedance from geometry Copper 1oz about 35um Applications 2 layer low speed 4 layer embedded 6 layer mixed signal RF high speed Design rules Confirm fabricator stack Keep solid reference Avoid plane gaps Document impedance Practical checks Layer order Dielectric thickness Copper weight Trace space limits Common mistakes Late stackup Split returns Wrong material No fab notes