Requirements and Board Architecture
Good PCB design starts before schematic capture. The first engineering task is to turn product needs into a board architecture: what the board must do, what connects to it, how power flows, what risks are likely, and how success will be verified.
Learning Objectives
By the end of this lesson, you should be able to write PCB requirements, partition a board into functional blocks, define interfaces, sketch a power tree, identify constraints, and create a verification plan before layout begins.
Requirements First
Capture requirements in measurable language. Avoid vague statements such as "low power" or "small board" unless they include targets.
Useful requirement categories:
- input voltage range and transients;
- maximum load current and duty cycle;
- operating temperature and storage temperature;
- mechanical envelope, mounting holes, connector locations;
- signal interfaces and data rates;
- accuracy, noise, timing, and latency;
- EMC, ESD, safety, isolation, or certification needs;
- production volume, cost target, and test method.
Architecture Block Diagram
This diagram is not layout. It is a communication tool that shows boundaries, power domains, and signal flow before component details hide the system intent.
Power Tree
Define every rail:
| Rail | Source | Loads | Current | Tolerance | Notes |
|---|---|---|---|---|---|
| VIN | Connector | Regulators, protection | 2 A max | 9 V to 36 V | transient-rated |
| 5V | Buck regulator | USB, sensors | 600 mA | +/-5% | switcher noise |
| 3V3 | LDO or buck | MCU, logic | 250 mA | +/-3% | ADC reference separated if needed |
| VREF | Reference IC | ADC reference | 2 mA | 0.1% | Kelvin route |
Power budgeting prevents under-sized regulators, overheated copper, and missing sequencing requirements.
Interface Definition
For each connector and internal interface, record:
- pinout and direction;
- voltage levels and tolerance;
- maximum current;
- cable length and environment;
- ESD and surge exposure;
- data rate and impedance needs;
- hot-plug expectations;
- test access.
The connector is often where real-world abuse enters the board. Treat it as a risk boundary.
Partitioning Rules
Group circuits by function and noise sensitivity:
- power entry and protection near the input connector;
- switching regulators away from sensitive analog inputs;
- high-speed interfaces with short controlled paths;
- analog front ends close to sensors or connector pins;
- clocks close to the device they serve;
- test points accessible after assembly.
Partitioning should reduce return-path confusion and make layout constraints obvious.
Risk Register
Create a short risk register before schematic:
| Risk | Cause | Mitigation | Verification |
|---|---|---|---|
| Regulator overheats | high VIN and load | efficiency estimate, thermal copper | thermal test |
| ADC noisy | shared switcher return | analog partition, filtering, reference plan | noise measurement |
| ESD reset | exposed connector | TVS, chassis path, firmware recovery | ESD test |
| Connector mismatch | unclear pinout | keyed connector, drawing review | first article inspection |
Common Mistakes
- Starting layout before requirements are measurable.
- Treating power as a list of regulators instead of a current and heat budget.
- Forgetting connector abuse, ESD, and cable effects.
- Mixing high-current, high-speed, and precision analog areas without return-path planning.
- Leaving production test access until the end.
Summary
PCB architecture translates product intent into engineering structure. A useful architecture defines requirements, blocks, rails, interfaces, constraints, risks, and verification before detailed schematic and layout work begin.
Further Reading
- IPC-2221, generic standard on printed board design.
- Analog Devices, "A Practical Guide to High-Speed Printed-Circuit-Board Layout."
- Texas Instruments, "Power Supply Design Seminar" materials.