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EMC, ESD, Grounding, and Layout

EMC design keeps a product from disturbing other equipment and helps it survive external noise. ESD design protects exposed interfaces from fast high-voltage discharge. Both depend heavily on current return paths and physical layout.

Learning Objectives

By the end of this lesson, you should be able to identify noise sources, plan return paths, place ESD protection, separate noisy and sensitive circuits, and review a PCB layout for EMC risk.

Noise Paths

flowchart LR S[Noise source] --> C1[Conducted path] S --> C2[Radiated path] C1 --> V[Victim circuit] C2 --> V V --> F[Failure: reset, ADC noise, comms error]

Noise requires a source, coupling path, and victim. Reduce any one of the three and the problem improves.

Common sources:

  • switching regulators;
  • motor and relay drivers;
  • fast digital clocks;
  • long cables;
  • ESD events;
  • poor return-path layout.

Return Paths

Every signal current returns to its source. At high frequency, return current follows the lowest impedance path, usually directly under the signal trace on the nearest continuous plane. If the return path is broken by a split plane, slot, or connector mistake, loop area grows and emissions increase.

Loop inductance creates voltage noise:

$$
V = L\frac{di}{dt}
$$

Fast current edges are often more troublesome than high current alone.

Grounding Strategy

Use a continuous ground reference for most mixed-signal embedded boards. Separate noisy and sensitive current paths by placement and routing, not by casually splitting ground.

Good practice:

  • put switching power and motor loops in their own compact area;
  • keep analog input returns quiet;
  • connect cable shields intentionally;
  • avoid routing high-speed signals over plane gaps;
  • use stitching vias near layer transitions.

ESD Protection

Place ESD protection close to the connector so surge current is diverted before it enters the board.

ESD path priority:

  1. connector pin;
  2. protection device;
  3. low-inductance return to chassis or ground strategy;
  4. protected internal signal.

A protection part with low capacitance is needed for high-speed USB or RF. A high-capacitance TVS may be fine for slow GPIO but can ruin signal integrity on fast lines.

Filtering at Cable Entry

For external signals, consider:

  • common-mode choke for differential communication;
  • RC filter for slow analog or GPIO;
  • ferrite bead for supply entry;
  • feedthrough capacitor or EMI filter for severe environments;
  • shield termination to chassis near entry.

Filter placement matters. A filter far from the connector lets noise travel across the board before being attenuated.

Layout Review Checklist

  • Are high di/dt loops compact?
  • Are input and output capacitors close to regulators?
  • Do fast signals have continuous return planes?
  • Are analog inputs away from switching nodes and inductors?
  • Are ESD devices at the connector?
  • Are differential pairs routed together with correct reference?
  • Are cable shields handled intentionally?
  • Are slots or plane cuts forcing return currents to detour?

Worked Example: Noisy ADC Near Buck Regulator

Symptom: ADC reading jumps when a buck regulator load changes.

Likely causes:

  • ADC input trace runs near switching node;
  • analog return shares pulsed regulator current;
  • insufficient input filtering;
  • reference decoupling is too far from ADC;
  • regulator hot loop is large.

Fixes:

  • move analog front end away from inductor and switch node;
  • shrink the buck input and catch-current loops;
  • add RC filter at ADC input;
  • place reference capacitor close to ADC reference pin;
  • route sensor return to quiet analog ground area.

Common Mistakes

  • Splitting ground without controlling where signals cross the split.
  • Placing ESD diodes far from connectors.
  • Routing clocks or switch nodes near sensor traces.
  • Assuming schematic correctness guarantees EMC performance.
  • Leaving cable shields floating without a reason.
  • Using long thin traces for surge current return.

Summary

EMC and ESD are layout-dependent system properties. Control loop area, return paths, cable entry, protection placement, grounding, shielding, and noisy-load placement early. Fixing EMC after the PCB is built is slower and less predictable than designing the current paths correctly from the start.

Further Reading

  • Henry Ott, Electromagnetic Compatibility Engineering.
  • Texas Instruments, "PCB Layout for EMC" application notes.
  • Analog Devices, "Grounding and Decoupling" tutorials.
  • IEC 61000-4-2 and IEC 61000-4-4 overviews for immunity context.

Mind Map

mindmap root((EMC ESD layout)) Core concept Control current paths Reduce coupling Protect entry points Applications Sensor boards Motor control Industrial ports RF products Formulas V equals L di over dt Loop area raises EMI Return follows impedance TVS capacitance matters Design rules ESD at connector Compact hot loops Continuous return plane Filter cable entry Practical checks Plane gaps Shield bond Switch node distance Surge return path Common mistakes Random ground split Late ESD placement Long return loop Noisy ADC routing