Memory and Storage

Embedded products store firmware, configuration, logs, calibration constants, keys, and user data. The right memory depends on capacity, speed, endurance, retention, power-fail behavior, interface, security, and cost.

Learning Objectives

By the end of this lesson, you should be able to compare common memory types, estimate endurance, choose a bus, add write protection, and design for power-fail data integrity.

Memory Types

Internal flash: stores firmware; limited erase/write cycles.
External NOR flash: code storage and fast random reads.
NAND flash or eMMC: high capacity, block management required.
EEPROM: small configuration storage, byte or page writes.
FRAM/MRAM: high endurance, good for frequent logging.
SRAM/PSRAM: volatile working memory.
SD card: removable mass storage, convenient but less deterministic.

Selection Criteria

flowchart LR A[Data need] --> B{Volatile?} B -->|Yes| C[SRAM or PSRAM] B -->|No| D{Capacity} D -->|Bytes to kB| E[EEPROM or FRAM] D -->|MB firmware| F[NOR flash] D -->|GB logs| G[eMMC or SD] E --> H[Check endurance] F --> I[Check erase sectors] G --> J[Check power fail]

Start with the data lifecycle: how often it changes, how long it must survive, and what happens if power fails during a write.

Endurance and Wear

Nonvolatile memory has finite write or erase cycles. If one record is updated too often, it can wear out.

Approximate lifetime:

$$
Lifetime = \frac{Cycles \times Slots}{Writes\ per\ day}
$$

For 100000 cycles, 64 rotating slots, and 100 writes per day:

$$
Lifetime = \frac{100000 \times 64}{100} = 64000\ days
$$

Without wear leveling, the same memory would last only 1000 days.

Flash Erase Blocks

Flash writes change bits in one direction and erase resets a full block or sector. This matters because updating one byte may require reading, erasing, and rewriting a larger sector.

Check:

erase sector size;
page program size;
maximum erase time;
write current;
read mode and dummy cycles;
boot support, such as memory-mapped QSPI.

Bus Choices

I2C EEPROM: simple, slower, small capacity.
SPI NOR flash: faster and common for firmware and logs.
QSPI/OSPI NOR: high throughput, memory-mapped execution possible.
Parallel SRAM: fast but many pins.
SDIO/eMMC: high capacity, more complex layout and firmware.

For SPI/QSPI flash, route clock and data with controlled impedance only when speeds demand it, keep traces short, and add series resistors if edges ring.

Write Protection and Security

Hardware write protection prevents accidental corruption:

tie WP# through a controllable pull;
use HOLD# or reset pins correctly;
protect boot flash during firmware update windows;
store keys in secure elements or MCU secure storage when required;
lock debug access for production if threat model demands it.

Do not rely only on firmware convention for critical calibration or boot data.

Power-Fail Integrity

Power loss during a write is a normal field event. Protect data with:

two-copy records with version counters;
CRC on every record;
commit marker written last;
brownout detection before write;
enough hold-up capacitance for the worst-case write time;
journaling or filesystem designed for flash.

Hold-up capacitance estimate:

$$
C \ge \frac{I \Delta t}{\Delta V}
$$

If a flash write needs 30 mA for 5 ms and voltage may fall by 0.3 V:

$$
C \ge \frac{0.03 \times 0.005}{0.3} = 500 \mu F
$$

This is an estimate; regulator dropout and load changes must also be checked.

Worked Example: Configuration EEPROM

A product stores calibration constants once at production and user settings up to 20 times per day. Data size is 128 bytes.

Use a small I2C EEPROM or FRAM:

EEPROM is acceptable if endurance is 1M cycles and writes are infrequent.
FRAM is better if logs or counters are updated often.
Add CRC and duplicate records.
Pull WP# active except during controlled updates.

Practical Checks

Verify voltage compatibility and level shifting for memory bus.
Check boot strapping if the MCU boots from external memory.
Confirm pull-ups for I2C EEPROM address pins and write protect.
Budget peak write current on the power rail.
Keep flash clock traces short and clean.
Test power interruption during writes.
Confirm data retention at maximum temperature.

Common Mistakes

Logging frequently to the same flash address.
Ignoring erase sector size.
Forgetting pull states on chip-select pins.
Using SD cards for deterministic hard real-time logs without buffering.
No CRC or versioning for configuration records.
Underestimating current during flash program or erase.

Summary

Memory design is about data lifetime, not just capacity. Select storage by volatility, endurance, speed, power-fail behavior, bus complexity, security, and layout needs. Use wear leveling, CRCs, write protection, and power-fail tests for data that must survive the field.

Mind Map

mindmap root((Memory storage)) Core concept Store firmware Store data Survive power loss Applications Boot flash Calibration Logs User files Formulas Lifetime equals cycles times slots over writes per day C hold up at least I dt over dV LSB not relevant CRC checks records Design rules Match memory type Respect erase blocks Add write protect Use duplicate records Practical checks Endurance Write current Data retention Bus signal quality Common mistakes No wear leveling No CRC Floating chip select Power fail corrupts data