Digital Interfaces and Level Shifting

Digital pins look simple until two devices disagree about voltage, direction, timing, or power state. A reliable embedded board defines every digital interface before schematic capture: signal owner, voltage level, current, speed, connector exposure, idle state, and fault behavior.

Learning Objectives

By the end of this lesson, you should be able to read logic-level specifications, decide when level shifting is required, choose common translator circuits, size pull resistors, and review digital interfaces for startup and hot-plug risks.

Logic-Level Compatibility

Logic compatibility is not decided by supply voltage alone. Compare the transmitter output specifications against the receiver input thresholds:

VOH(min): lowest guaranteed output-high voltage.
VOL(max): highest guaranteed output-low voltage.
VIH(min): minimum input voltage recognized as high.
VIL(max): maximum input voltage recognized as low.

The interface is compatible when:

$$
VOH(min) > VIH(min)
$$

$$
VOL(max) < VIL(max)
$$

Add margin for noise, ground offset, temperature, and cable drop.

Interface Inventory

Create an interface table during architecture work:

signal name and connector or device pin;
source and destination;
voltage domain, such as 1V8, 3V3, or 5V;
direction: input, output, bidirectional, open-drain, or tri-state;
idle level and reset state;
maximum frequency or edge rate;
pull-up or pull-down requirement;
protection, isolation, or level shifting requirement.

This table prevents late schematic surprises such as a 5 V sensor connected directly to a 3.3 V MCU pin.

Common Level-Shifting Choices

flowchart LR A[Signal need] --> B{Direction} B -->|One way| C[Divider or buffer] B -->|Bidirectional open drain| D[MOSFET I2C shifter] B -->|Fast push pull| E[Logic translator IC] B -->|No shared ground| F[Digital isolator] C --> G[Check speed and input current] D --> H[Check pullups and bus capacitance] E --> I[Check OE and power sequencing] F --> J[Check isolation rating]

Resistor Divider

A divider is acceptable for slow one-way signals into high-impedance inputs:

$$
V_{out} = V_{in}\frac{R_2}{R_1 + R_2}
$$

For 5 V to 3.3 V, R1 = 10 kOhm and R2 = 20 kOhm gives about 3.33 V. Do not use a divider for high-speed clocks, bidirectional buses, or outputs that must drive current.

MOSFET Open-Drain Shifter

The small-NMOS level shifter is common for I2C because both sides are open-drain and each side has its own pull-up. It is not correct for push-pull SPI clocks or UART transmit pins.

Translator IC

Use a proper logic translator for high-speed, push-pull, or multi-bit buses. Check:

supported voltage ranges;
direction control or auto-direction behavior;
output enable state during reset;
maximum data rate;
partial-power-down behavior.

Isolation

Use digital isolators or optocouplers when grounds may differ, external wiring is long, safety isolation is required, or high-energy equipment is nearby.

Pull-Up and Pull-Down Resistors

Pull resistors define an input when no device is actively driving it. They also set rise time for open-drain buses.

For a pull-up resistor:

$$
I_{LOW} = \frac{V_{PU}}{R_{PU}}
$$

For an RC rise approximation:

$$
t_r \approx 2.2R_{PU}C_{bus}
$$

Use stronger pull-ups for fast edges or high bus capacitance, but confirm devices can sink the resulting current.

Power Sequencing and Back-Powering

A powered-off IC can be damaged or unintentionally powered through an input protection diode. Check all interfaces where one side may be off while the other side is active.

Mitigations include:

translator with partial-power-down protection;
series resistor to limit injection current;
output-enable controlled by both power-good signals;
bus switches or load switches;
firmware reset states that keep pins high impedance.

Worked Review Example

A 5 V ultrasonic sensor drives an echo pin into a 3.3 V MCU. The sensor output is push-pull and slow, about 100 us pulses.

Use a divider:

R1 = 10 kOhm from sensor output to MCU input;
R2 = 20 kOhm from MCU input to ground;
output high is about 3.33 V;
divider current at high is 5 V / 30 kOhm = 0.167 mA.

Check the MCU VIH(min). If it is 0.7 x 3.3 V = 2.31 V, the high-level margin is about 1.02 V.

Practical Checks

Compare VOH/VOL against VIH/VIL, not only voltage labels.
Confirm reset and boot strapping pins have correct default levels.
Check pull-up current and rise time on open-drain buses.
Add series damping resistors for fast edges leaving the MCU.
Protect connector-facing pins from ESD and miswiring.
Confirm no input is driven while its device supply is off.

Common Mistakes

Using an I2C MOSFET shifter for SPI.
Forgetting that 5 V tolerant may apply only when the MCU is powered.
Leaving boot pins floating.
Using weak pull-ups on a long I2C cable.
Translating a clock through an auto-direction part that distorts edges.
Treating connector GPIO as safe without ESD protection.

Summary

Digital interface design is a voltage, timing, direction, and power-state problem. Review every signal against logic thresholds, reset state, pull resistor value, level-shifter behavior, speed, cable exposure, and powered-off conditions before the schematic is released.

Mind Map

mindmap root((Digital interfaces)) Core concept Match logic levels Define direction Control idle state Applications GPIO UART SPI I2C Connectors Formulas VOH greater than VIH VOL less than VIL Divider Vout equals Vin R2 over R1 plus R2 Rise time about 2.2 R C Design rules Pick correct shifter Protect exposed pins Avoid back power Set boot pulls Practical checks Threshold margin Pull current Bus capacitance Reset state Common mistakes Wrong shifter type Floating straps Weak pullups Ignoring off state