Finite-State Machines in Verilog

Finite-state machines control sequences: wait, start, transmit, finish, recover. A good FSM begins as a diagram, not as a long chain of if statements.

Learning Objectives

By the end of this lesson, you should be able to:

• identify when an FSM is the right structure;
• draw states and transitions before coding;
• write a Verilog FSM with next-state and state-register logic;
• avoid latch, reset, and unreachable-state mistakes.

When to Use an FSM

Use an FSM when the output depends on the current phase of an operation:

• UART transmit: idle, start bit, data bits, stop bit;
• SPI controller: idle, assert chip select, shift bits, finish;
• button debounce: idle, count stable time, accept, wait release;
• bus peripheral: wait request, respond, clear.

State Diagram First

Verilog FSM Template

localparam IDLE  = 2'd0;
localparam LOAD  = 2'd1;
localparam SHIFT = 2'd2;
localparam DONE  = 2'd3;

reg [1:0] state;
reg [1:0] next_state;

always @* begin
    next_state = state;
    done = 1'b0;

    case (state)
        IDLE: begin
            if (start)
                next_state = LOAD;
        end

        LOAD: begin
            next_state = SHIFT;
        end

        SHIFT: begin
            if (bit_count_done)
                next_state = DONE;
        end

        DONE: begin
            done = 1'b1;
            next_state = IDLE;
        end

        default: begin
            next_state = IDLE;
        end
    endcase
end

always @(posedge clk) begin
    if (rst)
        state <= IDLE;
    else
        state <= next_state;
end

The combinational block decides what should happen next. The clocked block stores the current state.

Moore vs Mealy Outputs

Beginners should usually start with Moore-style outputs unless the design clearly needs immediate input-dependent response.

Exercise

Design a Verilog FSM for a traffic light:

• NS_GREEN
• NS_YELLOW
• EW_GREEN
• EW_YELLOW

Inputs are timer-done signals. Outputs drive red/yellow/green for both roads. Draw the diagram first, then write the state encoding and transition logic.

Common Mistakes

• Coding states before drawing transitions.
• Missing default assignments in next-state logic.
• Forgetting reset state.
• Mixing output logic into too many scattered blocks.
• Letting an asynchronous input drive state transitions directly.

Summary

FSMs are the control skeleton of many FPGA systems. Draw the behavior first, then code next-state logic and a clocked state register clearly. Keep outputs deliberate and reviewable.

Next: Verilog Style for Synthesis.

Further Reading

• Vendor FSM coding templates
• Verilator lint warnings
• Yosys FSM optimization notes

Mind Map