Distinguish ISA, microarchitecture, ABI, and platform; compare register, encoding, privilege, and memory-model choices; decode a simple instruction; and select documentation for the exact profile and extensions in use.
You have learned that CISC and RISC are philosophies. Now let's meet the actual architectures that implement those philosophies — the Instruction Set Architectures (ISAs) that define every CPU ever built.
There is a critical distinction that most textbooks bury in a footnote. It separates how you think about processors from how they are built and sold:
An ISA is a contract between software and hardware.
The silicon that implements it is a completely separate thing.
Understanding this distinction is what separates an engineer from someone who just uses tools.
What Is an ISA?
An ISA defines everything software needs to know about a processor:
flowchart TD
classDef isa fill:#dbeafe,stroke:#1d4ed8,color:#1e3a8a
classDef sw fill:#dcfce7,stroke:#16a34a,color:#14532d
classDef hw fill:#ffedd5,stroke:#ea580c,color:#9a3412
classDef mid fill:#f3e8ff,stroke:#9333ea,color:#581c87
subgraph ISA_DEF ["What an ISA Specifies"]
I1["Instruction encoding\n(what bit patterns mean ADD, MOV, JMP...)"]:::isa
I2["Register set\n(how many, how wide, special-purpose?)"]:::isa
I3["Addressing modes\n(immediate, register, indirect, displacement...)"]:::isa
I4["Memory model\n(byte order, alignment, address width)"]:::isa
I5["Calling convention\n(how functions pass arguments)"]:::isa
I6["Privilege levels\n(user mode vs kernel mode)"]:::isa
I7["Exception and interrupt model\n(what happens on fault or IRQ)"]:::isa
end
SW["Software\n(OS, compiler, firmware)\nonly needs to know the ISA"]:::sw
ISA_DEF
HW["Hardware\n(transistors, gates, flip-flops)\ncan implement ISA any way it wants"]:::hw
SW -->|"writes to"| ISA_DEF
ISA_DEF -->|"implemented by"| HW
Software written for an ISA runs on any silicon that implements that ISA. This is why a program compiled for x86 runs on an Intel chip, an AMD chip, and a VIA chip — completely different transistors, same ISA.
The Most Important Distinction: ISA vs Microarchitecture
flowchart LR
classDef isa fill:#dbeafe,stroke:#1d4ed8,color:#1e3a8a
classDef uarch fill:#fee2e2,stroke:#dc2626,color:#7f1d1d
classDef silicon fill:#dcfce7,stroke:#16a34a,color:#14532d
subgraph ISABOX ["ISA — The Contract"]
direction TB
A1["ARM v8-A ISA\n(document, specification)"]:::isa
A2["RISC-V RV32I ISA\n(open standard)"]:::isa
A3["x86-64 ISA\n(Intel + AMD owned)"]:::isa
end
subgraph UARCH ["Microarchitecture — The Implementation"]
direction TB
B1["ARM Cortex-A78\n(ARM Ltd design)"]:::uarch
B2["Apple Firestorm\n(Apple design)"]:::uarch
B3["Samsung Mongoose\n(Samsung design)"]:::uarch
B4["Qualcomm Oryon\n(Qualcomm design)"]:::uarch
end
subgraph SILICON ["Silicon — The Chip"]
direction TB
C1["TSMC 5nm\n(Apple A14)"]:::silicon
C2["Samsung 4nm\n(Snapdragon 8 Gen 2)"]:::silicon
C3["TSMC 3nm\n(Apple A17 Pro)"]:::silicon
end
A1 -->|"licensed to"| B1
A1 -->|"licensed to"| B2
A1 -->|"licensed to"| B3
A1 -->|"licensed to"| B4
B2 --> C1
B4 --> C2
B2 --> C3
ARM Ltd designs the ISA and reference microarchitectures, but they do not own any fab. They license the ISA to Apple, Qualcomm, Samsung, and hundreds of others. Each company then designs their own transistor-level implementation. Apple's M-series chips implement the ARM ISA with Apple's own microarchitecture and have it manufactured at TSMC. ARM Ltd never touched the silicon.
This business model — fabless IP licensing — is one of the most successful in the history of technology.
Intel released the 8086 processor in 1978. It was a 16-bit CISC processor for personal computers. Nobody expected it to last 50 years. It did — because IBM chose it for the PC in 1981, and backward compatibility became a sacred law.
flowchart TD
classDef era16 fill:#fce7f3,stroke:#db2777,color:#831843
classDef era32 fill:#fee2e2,stroke:#dc2626,color:#7f1d1d
classDef era64 fill:#ffedd5,stroke:#ea580c,color:#9a3412
subgraph G16 ["16-bit Era"]
E1["8086 (1978)\n16-bit · 1 MB address space\nAX, BX, CX, DX registers\nIBM PC chose this in 1981"]:::era16
E2["80286 (1982)\n16-bit protected mode\n16 MB address space\nFirst multitasking support"]:::era16
end
subgraph G32 ["32-bit Era (IA-32)"]
E3["80386 (1985)\n32-bit · 4 GB address space\nAll 32-bit Windows/Linux apps\nrun on this ISA"]:::era32
E4["Pentium (1993)\nSuperscalar · FPU on-chip\n500 MHz by year 2000\nMMX / SSE added later"]:::era32
end
subgraph G64 ["64-bit Era (x86-64)"]
E5["x86-64 (2003)\n64-bit extension by AMD\n16 EB address space\n16 general-purpose registers"]:::era64
E6["Today — Core i9 / Ryzen 9\n~6 GHz · 24+ cores\nAVX-512 SIMD\nStill runs 1985 IA-32 binaries"]:::era64
end
G16 -->|"386 adds 32-bit"| G32
G32 -->|"AMD extends to 64-bit"| G64
Why x86 is CISC
flowchart TD
classDef bad fill:#fee2e2,stroke:#dc2626,color:#7f1d1d
classDef good fill:#dcfce7,stroke:#16a34a,color:#14532d
classDef neutral fill:#f1f5f9,stroke:#475569,color:#1e293b
subgraph XPROS ["x86 Strengths"]
P1["Dense code — programs are compact\n(variable-length instructions 1–15 bytes)"]:::good
P2["Massive software ecosystem\n(every OS, every language, 50 years of libraries)"]:::good
P3["Extremely fast implementations\n(modern CPUs translate x86 to internal RISC µops)"]:::good
P4["Dominates servers and desktops\n(AWS, Azure, Google Cloud all run x86)"]:::good
end
subgraph XCONS ["x86 Weaknesses"]
C1["Complex decoder hardware\n(15-byte variable-length instructions)"]:::bad
C2["High power consumption\n(complexity has a cost)"]:::bad
C3["Not suitable for embedded\n(minimum chip size is large)"]:::bad
C4["Intel + AMD control it\n(proprietary, licensing required)"]:::bad
end
Modern x86 is secretly RISC inside. Intel and AMD processors decode x86 instructions into simpler internal micro-operations (µops) that execute on a RISC-style pipeline. The x86 ISA is the public interface; the internal implementation is RISC. This is the cost of 50 years of backward compatibility.
x86-64 (x64 / AMD64) — The 64-bit Extension
In 2003, AMD — not Intel — released the first 64-bit extension of x86, called AMD64. Intel had their own incompatible 64-bit architecture (IA-64 / Itanium) that failed in the market. Intel eventually adopted AMD64 and called it Intel 64 or EM64T. Today it is known as x86-64 or simply x64.
flowchart TD
classDef old fill:#fee2e2,stroke:#dc2626,color:#7f1d1d
classDef new fill:#dcfce7,stroke:#16a34a,color:#14532d
classDef both fill:#dbeafe,stroke:#1d4ed8,color:#1e3a8a
subgraph IA32 ["IA-32 (32-bit x86)"]
R1["8 general-purpose registers\nEAX, EBX, ECX, EDX\nESI, EDI, ESP, EBP\n(each 32-bit)"]:::old
R2["4 GB maximum RAM\n(32-bit address space)"]:::old
R3["32-bit pointers"]:::old
end
subgraph X64 ["x86-64 additions"]
R4["16 general-purpose registers\nRAX–RDX, RSI, RDI, RSP, RBP\n+ R8–R15\n(each 64-bit)"]:::new
R5["16 EB maximum RAM\n(48-bit address used in practice → 256 TB)"]:::new
R6["64-bit pointers\n(8 bytes per pointer)"]:::new
R7["16 XMM/YMM/ZMM SIMD registers\n(for floating point and vector math)"]:::new
end
COMPAT["Full backward compatibility\nA 32-bit x86 binary still runs\non any x86-64 CPU today"]:::both
IA32 --> X64
X64 --> COMPAT
When you compile a C program on Linux with gcc -m32 vs gcc -m64, you are targeting IA-32 vs x86-64 respectively. The calling conventions, register names, and ABI are different — but the underlying ISA is a superset.
8051 — The Cockroach of Microcontrollers
The Intel MCS-51 (8051) was released in 1980 for industrial control systems. Intel sold the design to dozens of companies. It is still manufactured today by NXP, Silicon Labs, STMicroelectronics, and others. More 8051-compatible chips are sold each year than x86 chips.
flowchart TD
classDef core fill:#fce7f3,stroke:#db2777,color:#831843
classDef mem fill:#f3e8ff,stroke:#9333ea,color:#581c87
classDef per fill:#ffedd5,stroke:#ea580c,color:#9a3412
classDef weak fill:#fee2e2,stroke:#dc2626,color:#7f1d1d
subgraph ISA8051 ["8051 ISA Characteristics"]
direction TB
C1["8-bit data bus\n1 accumulator (A) as primary register\nB register for multiply/divide only"]:::core
C2["8 general Rn registers\n(R0–R7, but only one bank active at a time)"]:::core
C3["Separate code and data address spaces\n(Harvard-like, but quirky)\nMOVC for code, MOVX for external data"]:::mem
C4["Bit-addressable memory region\n(0x20–0x2F — individual bits have addresses)"]:::mem
C5["Compact instruction set\n(111 instructions, 1–3 bytes each)"]:::core
C6["Boolean processor built-in\n(SETB, CLR, CPL on individual bits)"]:::per
end
subgraph WHY8051 ["Why it Survives"]
W1["✅ Extremely low silicon cost\n(simple design → tiny die area)"]:::per
W2["✅ Deterministic timing\n(12 clock cycles per instruction — predictable)"]:::per
W3["✅ 45 years of tools, libraries, engineers"]:::per
W4["✅ Single-cycle variants exist\n(modern 8051 cores run at 1 CPI)"]:::per
W5["❌ Accumulator bottleneck\n(every operation goes through A)"]:::weak
W6["❌ Limited register file\n(only 8 working registers)"]:::weak
end
Where you find 8051 today: USB controllers (every Cypress FX2), automotive body control modules, cheap wireless chips (CC2540 BLE = 8051 + radio), medical devices, industrial sensors. When something only needs to read one sensor and toggle one relay — cost wins.
AVR — Born for C Compilers
Atmel's AVR (1996) was the first microcontroller architecture designed from day one with C compiler optimization as a primary goal. The two designers (Alf-Egil Bogen and Vegard Wollan — "AV" + "R") studied what compilers need and built the ISA to match.
flowchart LR
classDef feat fill:#dcfce7,stroke:#16a34a,color:#14532d
classDef chip fill:#dbeafe,stroke:#1d4ed8,color:#1e3a8a
subgraph AVR_ISA ["AVR ISA Design Goals"]
A1["32 × 8-bit general purpose registers\n(R0–R31 — compiler has room to work)"]:::feat
A2["All instructions 16-bit (1 word)\nExcept LDS/STS/JMP/CALL (2 words)\n→ fixed-length, easy to fetch and decode"]:::feat
A3["Most instructions execute in 1 clock cycle\n→ performance equals clock frequency"]:::feat
A4["Harvard architecture\nFlash for program, SRAM for data\n→ maps perfectly to MCU constraints"]:::feat
A5["Load/Store ISA\nALU only works on registers\n→ simple, pipelinable"]:::feat
A6["Pointer registers X, Y, Z (R27:R26, R29:R28, R31:R30)\nPost-increment, pre-decrement, displacement\n→ efficient array and struct access"]:::feat
end
subgraph AVR_FAMILY ["AVR Family"]
T1["ATtiny\n(0.5–32 KB Flash\n≤ 32 pins\nSimple tasks)"]:::chip
T2["ATmega\n(4–256 KB Flash\nFull peripheral set\nArduino Uno = ATmega328P)"]:::chip
T3["ATxmega\n(16–384 KB Flash\nDMA, event system\nAdvanced applications)"]:::chip
T4["AVR DA/DB/DD series\n(Modern, low power\nCLC, OPAMP, Core Independent Peripherals)"]:::chip
end
Microchip Technology acquired Atmel in 2016. The AVR architecture continues in production and is the foundation of Arduino.
ARM — The Architecture That Powers Everything Portable
ARM (originally Acorn RISC Machine, 1985 — later Advanced RISC Machine) is the most successful processor architecture in history by unit volume. It is in your phone, your router, your smart TV, your car, and since 2020, your Mac.
flowchart TD
classDef biz fill:#dbeafe,stroke:#1d4ed8,color:#1e3a8a
classDef profile fill:#dcfce7,stroke:#16a34a,color:#14532d
classDef chip fill:#f3e8ff,stroke:#9333ea,color:#581c87
classDef fab fill:#ffedd5,stroke:#ea580c,color:#9a3412
ARMLTD["ARM Ltd\n(Cambridge, UK)\nDesigns ISA + reference microarchitectures\nDoes NOT manufacture chips\nSells licenses"]:::biz
subgraph PROFILES ["ARM ISA Profiles"]
direction LR
CM["Cortex-M profile\n(microcontrollers)\nCortex-M0/M0+/M3/M4/M7/M33/M55\nThumb-2 instruction set\nNo MMU (usually)\nDeterministic, low latency"]:::profile
CA["Cortex-A profile\n(application processors)\nCortex-A5/A7/A53/A72/A78/X4\nFull AArch32/AArch64 ISA\nMMU — runs Linux/Android/iOS"]:::profile
CR["Cortex-R profile\n(real-time)\nCortex-R4/R5/R52\nMPU (not full MMU)\nAutomotive safety, hard disk controllers"]:::profile
end
subgraph LICENSEES ["Who Licenses ARM ISA"]
direction LR
L1["Apple\n(M1/M2/M3/M4, A-series)\nCustom microarchitecture\nMade by TSMC"]:::chip
L2["Qualcomm\n(Snapdragon)\nCustom Oryon cores\nMade by TSMC/Samsung"]:::chip
L3["Samsung\n(Exynos)\nCustom + standard Cortex\nMade in-house"]:::chip
L4["STMicroelectronics\n(STM32)\nStandard Cortex-M cores\nMade in-house + TSMC"]:::chip
L5["Nordic Semiconductor\n(nRF52/nRF91)\nCortex-M + radio\nMade at TSMC"]:::chip
L6["Raspberry Pi\n(RP2040, BCM2xxx)\nCortex-M0+ and Cortex-A\nMade at TSMC/Samsung"]:::chip
end
ARMLTD --> PROFILES
PROFILES --> LICENSEES
ARM's Business Model — Fabless IP
flowchart LR
classDef money fill:#fef9c3,stroke:#ca8a04,color:#713f12
classDef design fill:#dbeafe,stroke:#1d4ed8,color:#1e3a8a
classDef make fill:#dcfce7,stroke:#16a34a,color:#14532d
ARM["ARM Ltd\nDesigns ISA + CPU cores\nCharges per-unit royalty\n+ upfront license fee"]:::money
CHIPCO["Chip Company\n(Apple, Qualcomm, ST...)\nLicenses ARM ISA\nDesigns rest of chip\n(RAM, peripherals, bus)\nPays ARM royalty per chip sold"]:::design
FAB["Semiconductor Fab\n(TSMC, Samsung, GlobalFoundries)\nManufactures the physical chips\nCharges per wafer"]:::make
ARM -->|"license + IP"| CHIPCO
CHIPCO -->|"design files (GDSII)"| FAB
FAB -->|"finished chips"| CHIPCO
Arm's licensing and royalty terms vary by agreement. Architecturally, Arm supplies architecture and processor IP while licensees integrate products and manufacture through their chosen foundries.
Arm Holdings was acquired by SoftBank in 2016, attempted to be sold to Nvidia in 2022 (blocked by regulators), then IPO'd on Nasdaq in 2023 (ticker: ARM). It remains the most influential CPU architecture company that most people have never heard of.
RISC-V — The Open Architecture
Every ISA above is either owned by one company (x86 by Intel/AMD, AVR by Microchip, ARM by Arm Holdings) or no longer maintained (MIPS, PowerPC). If that company raises prices, goes bankrupt, or refuses to license to your country, you have no alternative.
RISC-V was created at UC Berkeley in 2010 specifically to fix this problem.
flowchart TD
classDef open fill:#fef9c3,stroke:#ca8a04,color:#713f12
classDef mod fill:#dcfce7,stroke:#16a34a,color:#14532d
classDef chip fill:#dbeafe,stroke:#1d4ed8,color:#1e3a8a
classDef risk fill:#fee2e2,stroke:#dc2626,color:#7f1d1d
subgraph RISCV_PROPS ["RISC-V Properties"]
direction TB
R1["Open standard\nPublished by RISC-V International\n(not-for-profit, Switzerland)\nNo royalties. No license fees. Ever."]:::open
R2["Modular base + extensions\nRV32I — 32-bit integer base (47 instructions)\nM — multiply/divide\nA — atomic operations\nF/D — floating point\nC — compressed 16-bit instructions\nV — vector operations\nCustom extensions allowed"]:::mod
R3["Designed for everything\n8-bit MCU to 64-bit server\nSame ISA, different widths (RV32/RV64/RV128)"]:::open
R4["Hardware open-source implementations\nPicoRV32, VexRiscv, CVA6\nReady to synthesize on FPGA today"]:::chip
end
subgraph RISCV_WHO ["Who Uses RISC-V"]
direction LR
W1["SiFive\n(commercial RISC-V chips\nfor embedded and HPC)"]:::chip
W2["Western Digital\n(all internal storage controllers\nswitched to RISC-V)"]:::chip
W3["Espressif\n(ESP32-C3 — Wi-Fi MCU\nfirst popular RISC-V IoT chip)"]:::chip
W4["Indian Space Research Org (ISRO)\nIndian defence electronics\n(sovereignty — no foreign ISA royalty)"]:::chip
W5["China\n(Alibaba T-Head, many others\nAvoiding ARM export restrictions)"]:::chip
W6["NVIDIA\n(internal microcontrollers\nin GPU firmware)"]:::chip
end
Why RISC-V Matters for You
flowchart LR
classDef you fill:#f3e8ff,stroke:#9333ea,color:#581c87
classDef fpga fill:#dbeafe,stroke:#1d4ed8,color:#1e3a8a
classDef future fill:#dcfce7,stroke:#16a34a,color:#14532d
YOU["You — learning embedded systems"]:::you
UNDERSTAND["Understand the ISA\n(this lesson — you are here)"]:::you
ASSEMBLY["Write RISC-V assembly\n(same concepts as AVR,\ndifferent mnemonics)"]:::you
IMPL["Implement RV32I on FPGA\n(synthesize a real CPU\nfrom scratch in Verilog/VHDL)"]:::fpga
RUN["Run C programs\non your own CPU\n(the full stack — your gates,\nyour ISA, your compiler output)"]:::future
YOU --> UNDERSTAND --> ASSEMBLY --> IMPL --> RUN
Coming in the FPGA lessons: You will implement the RV32I base integer ISA on an FPGA using Verilog. This means building the fetch-decode-execute pipeline, the ALU, the register file, and the memory interface — all from scratch — and then running real C code on a CPU you designed yourself. RISC-V makes this possible without license fees or legal restrictions.
This is not just technical trivia. Who owns the ISA determines who controls your supply chain.
flowchart TD
classDef risk fill:#fee2e2,stroke:#dc2626,color:#7f1d1d
classDef ok fill:#dcfce7,stroke:#16a34a,color:#14532d
classDef warn fill:#fef9c3,stroke:#ca8a04,color:#713f12
Q["Who controls the ISA?"]
Q --> INTEL["Intel / AMD control x86\n→ Want to make an x86 chip?\nNeed a license. Good luck."]:::risk
Q --> ARMHLD["Arm Holdings controls ARM\n→ License costs money\n→ Export controls apply\n→ If Arm raises prices, you pay"]:::warn
Q --> MCHP["Microchip owns AVR\n→ You can use AVR chips\n→ You cannot make AVR-compatible chips\nwithout a license"]:::warn
Q --> RISCVI["RISC-V International\n(not-for-profit, neutral)\n→ ISA is published, irrevocable, royalty-free\n→ Anyone can implement it\n→ No export controls on the ISA itself\n→ Used by India, China, EU for strategic independence"]:::ok
RISC-V's open ISA reduces dependence on a proprietary instruction-set license. Implementations, tools, semiconductor manufacturing, and third-party IP can still be subject to licenses and export controls.
Summary
Key Takeaways
An ISA defines programmer-visible instructions, registers, privilege, and memory behavior; an ABI separately defines calling and binary conventions
Microarchitecture is the transistor-level implementation of an ISA. Many different microarchitectures can implement the same ISA
x86 / x86-64 — CISC, Intel + AMD proprietary, dominates desktops and servers. Variable-length instructions, massive backward-compatible ecosystem
8051 — CISC, Intel's 1980 MCU architecture now widely cloned. Still sold billions of units per year due to extreme simplicity and low cost
AVR — RISC, Microchip (Atmel), 8-bit MCU ISA designed for C compilers. Foundation of Arduino
ARM — RISC, designed by Arm Ltd (fabless IP company), licensed to chip companies worldwide. Arm designs the ISA but does not manufacture silicon — Apple, Qualcomm, ST, Nordic, and others do
RISC-V — RISC, open standard, royalty-free, governed by a neutral non-profit. No license fees, no export controls on the ISA, anyone can implement it
Coming in FPGA lessons: You will implement the RV32I base ISA on an FPGA — building a real working CPU from logic gates up, running actual compiled C code on hardware you designed
Worked Decode Example
RISC-V addi x5, x6, 12 uses the I-type format: opcode 0010011, destination x5, function field 000, source x6, and a signed 12-bit immediate. Its effect is (x5 \leftarrow x6 + 12), wrapping modulo (2^{XLEN}). The encoding defines behavior; a microarchitecture may execute it in one stage or many.
Before decoding bytes, confirm XLEN, enabled extensions, privilege level, and byte order.
Common Mistakes
Using architecture, ISA, microarchitecture, ABI, and product family interchangeably.
Assuming every Arm processor supports identical instructions and privilege features.
Ignoring RISC-V extension requirements after software is compiled.
Comparing register counts without ABI-reserved roles.
Assuming an open ISA makes every core, tool, or chip open source.
mindmap
root((ISA))
Core concept
Software hardware contract
Microarchitecture implements ISA
ABI defines binary convention
Applications
x86 desktop and server
Arm embedded and mobile
AVR and 8051 control
RISC V custom systems
Calculations
Address space equals 2 power bits
Addi wraps modulo 2 power XLEN
Fields select operation
Design rules
Confirm profile and mode
List required extensions
Match compiler ABI
Read exact revision
Practical checks
Decode known instruction
Inspect ELF attributes
Check privilege support
Verify endianness
Common mistakes
ISA equals ABI
Family means one ISA
Open ISA means open chip
Ignoring extensions