PWM as a DAC and Filtering
Pulse-width modulation can approximate an analog output by switching a digital pin quickly and filtering the average value. This is useful when a microcontroller lacks a DAC or when the output only needs moderate accuracy and bandwidth. The design tradeoff is simple: lower ripple usually means slower response.
Learning Objectives
By the end of this lesson, you should be able to:
- calculate PWM average voltage from duty cycle;
- relate timer resolution to duty-cycle step size;
- choose a first-order RC filter cutoff;
- explain ripple, settling time, and load effects;
- verify a PWM-based analog output safely.
PWM Average Value
For a PWM waveform switching between 0 V and V_HIGH, the average value is:
$$
V_\text{AVG}=D V_\text{HIGH}
$$
where D is duty cycle from 0 to 1.
A 3.3 V PWM at 40% duty cycle has:
$$
V_\text{AVG}=0.40\times3.3=1.32\ \text{V}
$$
title "PWM duty changes average voltage"
time start=0 end=4 unit=ms divisions=4
PWM25: square label="25 percent duty" low=0 high=3.3 duty=25 cycles=4 unit=V color=#2563eb
PWM75: square label="75 percent duty" low=0 high=3.3 duty=75 cycles=4 unit=V color=#dc2626
The waveform is idealized and does not include pin rise time or load effects.
Timer Resolution
If a timer counts from 0 to TOP, it has TOP + 1 duty steps. Approximate PWM resolution is:
$$
N_\text{bits}=\log_2(TOP+1)
$$
A timer with TOP = 999 has 1000 steps, about:
$$
\log_2(1000)=9.97\ \text{bits}
$$
Raising PWM frequency often lowers resolution because the timer has fewer clock counts per period.
RC Low-Pass Filter
A first-order RC filter has cutoff frequency:
$$
f_c=\frac{1}{2\pi RC}
$$
Choose f_c much lower than the PWM carrier frequency to reduce ripple, but high enough for the desired output response.
Example: R = 10 kOhm, C = 1 uF:
$$
f_c=\frac{1}{2\pi(10000)(1\times10^{-6})}=15.9\ \text{Hz}
$$
That is suitable for a slow setpoint, not for audio or fast control.
Ripple and Response Tradeoff
A lower cutoff reduces PWM ripple but increases settling time. First-order settling to about 1% takes roughly:
$$
t_{1%}\approx4.6RC
$$
For 10 kOhm and 1 uF, RC = 10 ms, so 1% settling is about 46 ms.
Loading and Buffering
The load resistance appears in parallel with the filter capacitor and can change both output voltage and filter behavior. Use an op-amp buffer when the load is not very high impedance or when the output drives another circuit that injects noise.
The PWM pin also has current limits. Do not drive motors, relays, solenoids, or power stages directly from a filtered GPIO.
Verification Steps
- Measure raw PWM frequency and duty cycle with an oscilloscope or logic analyzer.
- Measure filtered DC output at several duty cycles.
- Check ripple at the filter output under real load.
- Step duty cycle and measure settling time.
- Verify startup duty cycle before the load is enabled.
- Confirm the output stays inside the receiving circuit range.
Common Mistakes
- Expecting a filtered PWM output to be a precision DAC.
- Choosing a cutoff near the PWM frequency and getting high ripple.
- Choosing a very low cutoff and getting sluggish response.
- Ignoring load resistance.
- Forgetting timer resolution loss at high PWM frequency.
Summary
PWM plus a low-pass filter can generate an analog-like voltage where moderate ripple and response time are acceptable. The key formulas are V_AVG = D V_HIGH, f_c = 1/(2 pi R C), and t_1% approx 4.6RC. Verify duty cycle, ripple, settling, load effects, and startup behavior before connecting actuators or references.
Further Reading
- Microchip: PWM Overview
- Texas Instruments: PWM DAC Using Low-Pass Filter
- Analog Devices: PWM DAC Design