DAC Fundamentals
A digital-to-analog converter turns a numeric code into a controlled voltage or current. DACs generate bias voltages, calibration trims, actuator setpoints, audio, test waveforms, and programmable references. A useful DAC design is not just a formula; it also needs a stable reference, a compatible output buffer, defined startup behavior, filtering where needed, and load verification.
Learning Objectives
By the end of this lesson, you should be able to:
- calculate ideal DAC output voltage from code;
- explain reference, resolution, settling time, and output range;
- identify buffering and load requirements;
- understand glitches and update timing;
- verify a DAC output in an embedded system.
Ideal DAC Transfer
For an ideal unipolar N-bit DAC with reference V_REF, the endpoint convention matters. Many voltage-output DAC datasheets use an endpoint code range from 0 to 2^N - 1:
$$
V_\text{OUT}=\frac{\text{code}}{2^N-1}V_\text{REF}
$$
The ideal code spacing is:
$$
\text{LSB}\text{endpoint}=\frac{V\text{REF}}{2^N-1}
$$
Some converter discussions approximate the LSB as:
$$
\text{LSB}\text{ideal}\approx\frac{V\text{REF}}{2^N}
$$
For a 12-bit DAC with 3.3 V reference:
$$
\text{LSB}_\text{endpoint}=\frac{3.3}{4095}=0.806\ \text{mV}
$$
Code 2048 gives:
$$
V_\text{OUT}=\frac{2048}{4095}\times3.3=1.6504\ \text{V}
$$
That is very close to mid-scale, but the exact value depends on the datasheet's transfer convention.
Output Range
Not every DAC can reach exactly 0 V or V_REF, especially when powered from a single supply and driving a load. Datasheets specify output swing, load resistance, load capacitance, and sometimes short-circuit behavior.
| Output type | Common use | Watch out |
|---|---|---|
| voltage output | MCU DAC, setpoints | output current and rail swing |
| current output | precision and high speed | needs transimpedance stage |
| multiplying DAC | programmable gain and references | reference input bandwidth |
| bipolar DAC | plus/minus outputs | supply rails and offset |
Buffering
A DAC output buffer isolates the converter from the load. Use a buffer or driver when the load is low resistance, capacitive, noisy, remote, or needs more current than the DAC can supply.
Choose an op amp with input/output range, bandwidth, slew rate, stability, offset, and load drive that fit the signal.
For a buffered voltage-output DAC, check:
- DAC output can drive the op-amp input capacitance and bias current error is acceptable;
- op-amp input common-mode range includes the full DAC swing;
- op-amp output swing reaches the required load voltage with margin;
- slew rate supports the largest expected step;
- capacitive loads use isolation resistance or a stable driver when the datasheet requires it.
Settling Time and Glitches
Settling time is the time required for the DAC output to reach and stay within a specified error band after a code change. A full-scale step takes longer than a small step.
A DAC can also produce glitch energy when internal switches change state. Glitches are most visible around major carry transitions such as mid-scale, where many bits switch at once.
For an N-bit DAC, half an LSB error band is:
$$
\frac{1}{2}\text{LSB}=\frac{V_\text{REF}}{2(2^N-1)}
$$
A 12-bit, 3.3 V DAC has a half-LSB band of about 0.403 mV. A datasheet settling specification such as "settles to 1/2 LSB in 10 us" means the output must enter and remain inside that final error window after the code step.
Waveform Generation
DAC waveform quality depends on update rate, reconstruction filtering, code resolution, clock jitter, and output amplifier bandwidth.
title "Stepped DAC approximation"
time start=0 end=10 unit=ms divisions=5
IDEAL: sine label="desired waveform" amplitude=1 cycles=1 unit=norm color=#2563eb
STEP: square label="sampled updates" low=-0.7 high=0.7 duty=50 cycles=5 unit=norm color=#dc2626
The stepped trace is illustrative, not a simulated DAC output.
Verification Steps
- Output
0, mid-scale, and full-scale codes and measure voltage. - Measure the DAC reference pin during static output and during updates.
- Check output with the real load connected.
- Step between two codes and observe settling on an oscilloscope.
- Repeat a mid-scale major-carry transition and look for glitches.
- Confirm firmware writes use the correct alignment, channel, trigger, and data format.
- Test reset and startup state so the connected actuator does not move unexpectedly.
Debugging Symptoms
| Symptom | Likely cause | First check |
|---|---|---|
| output is scaled wrong | reference or code alignment error | read back code format and measure V_REF |
| output clips near rails | buffer output swing limit | compare load voltage with op-amp datasheet |
| output rings after steps | capacitive load instability | add series isolation resistor and probe load |
| waveform has tones or jitter | irregular update timing | inspect timer/DMA trigger timing |
| actuator jumps at boot | unsafe default code | scope reset, enable, and DAC output pins |
Common Mistakes
- Assuming full-scale code equals exactly the supply rail.
- Driving a heavy load directly from a weak DAC output.
- Ignoring op-amp stability with capacitive loads.
- Updating the DAC with jittery firmware timing for waveform generation.
- Forgetting safe startup value for actuators and power electronics.
Summary
A DAC maps digital codes to analog output relative to a reference. Resolution gives code spacing, but practical output quality depends on reference accuracy, output swing, load drive, settling, glitches, filtering, and firmware timing. Verify the output under real load and define safe startup behavior.