DAC Fundamentals
A digital-to-analog converter turns a number into a voltage or current. DACs generate references, audio, bias voltages, setpoints, waveforms, calibration trims, and actuator commands. A useful DAC design needs correct code scaling, a stable reference, output buffering, filtering, and load checks.
Learning Objectives
By the end of this lesson, you should be able to:
- calculate ideal DAC output voltage from code;
- explain reference, resolution, settling time, and output range;
- identify buffering and load requirements;
- understand glitches and update timing;
- verify a DAC output in an embedded system.
Ideal DAC Transfer
For an ideal unipolar N-bit DAC with reference V_REF:
$$
V_\text{OUT}=\frac{\text{code}}{2^N-1}V_\text{REF}
$$
The ideal LSB is approximately:
$$
\text{LSB}=\frac{V_\text{REF}}{2^N}
$$
For a 12-bit DAC with 3.3 V reference, one LSB is about 0.805 mV. Code 2048 produces approximately mid-scale.
Output Range
Not every DAC can reach exactly 0 V or V_REF, especially when powered from a single supply and driving a load. Datasheets specify output swing, load resistance, load capacitance, and sometimes short-circuit behavior.
| Output type | Common use | Watch out |
|---|---|---|
| voltage output | MCU DAC, setpoints | output current and rail swing |
| current output | precision and high speed | needs transimpedance stage |
| multiplying DAC | programmable gain and references | reference input bandwidth |
| bipolar DAC | plus/minus outputs | supply rails and offset |
Buffering
A DAC output buffer isolates the converter from the load. Use a buffer or driver when the load is low resistance, capacitive, noisy, remote, or needs more current than the DAC can supply.
Choose an op amp with input/output range, bandwidth, slew rate, stability, offset, and load drive that fit the signal.
Settling Time and Glitches
Settling time is the time required for the DAC output to reach and stay within a specified error band after a code change. A full-scale step takes longer than a small step.
A DAC can also produce glitch energy when internal switches change state. Glitches are most visible around major carry transitions such as mid-scale, where many bits switch at once.
Waveform Generation
DAC waveform quality depends on update rate, reconstruction filtering, code resolution, clock jitter, and output amplifier bandwidth.
title "Stepped DAC approximation"
time start=0 end=10 unit=ms divisions=5
IDEAL: sine label="desired waveform" amplitude=1 cycles=1 unit=norm color=#2563eb
STEP: square label="sampled updates" low=-0.7 high=0.7 duty=50 cycles=5 unit=norm color=#dc2626
The stepped trace is illustrative, not a simulated DAC output.
Verification Steps
- Output
0, mid-scale, and full-scale codes and measure voltage. - Check output with the real load connected.
- Step between two codes and observe settling on an oscilloscope.
- Verify reference voltage while the DAC updates.
- Confirm firmware writes use the correct alignment and channel.
- Test startup state so the connected actuator does not move unexpectedly.
Common Mistakes
- Assuming full-scale code equals exactly the supply rail.
- Driving a heavy load directly from a weak DAC output.
- Ignoring op-amp stability with capacitive loads.
- Updating the DAC with jittery firmware timing for waveform generation.
- Forgetting safe startup value for actuators and power electronics.
Summary
A DAC maps digital codes to analog output relative to a reference. Resolution gives code spacing, but practical output quality depends on reference accuracy, output swing, load drive, settling, glitches, filtering, and firmware timing. Verify the output under real load and define safe startup behavior.