ADC Timing and Throughput

ADC timing decides whether firmware receives valid samples at the right moments. A converter may advertise a maximum sample rate, but the useful throughput depends on acquisition time, conversion time, channel switching, filtering latency, interrupt overhead, DMA buffering, and the analog source settling fast enough.

Learning Objectives

By the end of this lesson, you should be able to:

distinguish acquisition time, conversion time, throughput, and latency;
estimate sample timing for multiplexed ADC channels;
explain why source impedance affects acquisition;
identify jitter and trigger timing problems;
choose interrupt, polling, or DMA transfer strategies.

Timing Terms

Term	Meaning
acquisition time	time allowed for input sampling capacitor to settle
conversion time	time ADC core needs to produce the code
sample period	time between samples on one channel
throughput	usable output samples per second
latency	delay from analog event to available digital result

For a simple SAR ADC sequence:

$$
T_\text{sample}=T_\text{acq}+T_\text{conv}+T_\text{overhead}
$$

$$
f_\text{sample}=\frac{1}{T_\text{sample}}
$$

Acquisition and Settling

A SAR ADC input often looks like a switch and small capacitor. When the sample switch closes, the external source must charge the capacitor to the input voltage. High source resistance needs more acquisition time.

A first-order settling estimate uses:

$$
V_\text{error}=V_\text{step}e^{-t/(RC)}
$$

For N-bit settling to within about 0.5 LSB, a common estimate is:

$$
t \ge (N+1)\ln(2)RC
$$

For 12-bit settling, that is about 9RC.

Multiplexed Channels

When one ADC scans many channels, total scan time matters:

$$
T_\text{scan}=\sum(T_\text{acq,ch}+T_\text{conv,ch})+T_\text{sequence overhead}
$$

A high-impedance temperature input may need a long sample time, while a buffered current input may allow a short sample time. Many MCUs let each channel use a different acquisition setting.

sequenceDiagram participant TIM as Timer Trigger participant ADC as ADC Sequencer participant DMA as DMA Buffer participant FW as Firmware TIM->>ADC: start scan ADC->>ADC: acquire CH0 ADC->>ADC: convert CH0 ADC->>ADC: acquire CH1 ADC->>ADC: convert CH1 ADC->>DMA: write samples DMA->>FW: half/full buffer interrupt

Triggering and Jitter

Timer-triggered ADC sampling gives more consistent timing than starting conversions from a busy main loop. Jitter is sample-time uncertainty. It matters most for high-frequency signals because timing error becomes amplitude error.

For a sine wave, jitter-limited SNR is approximately:

$$
\text{SNR}\text{jitter}=-20\log{10}(2\pi f_\text{in}t_j)
$$

where t_j is RMS jitter in seconds.

Interrupts, Polling, and DMA

Method	Good for	Watch out
polling	simple slow readings	wastes CPU and timing varies
interrupt per sample	moderate rates	ISR overhead and latency
DMA circular buffer	steady high-rate streams	buffer ownership and cache coherency
hardware averaging	noise reduction	bandwidth and step response

DMA is usually the right choice for continuous multi-channel acquisition because it separates sample timing from firmware scheduling.

Latency in Delta-Sigma ADCs

Delta-sigma ADCs include digital filters. The output data rate may be 1 kS/s, but a step input can take several output periods to settle depending on filter type. For control loops, check group delay and step response, not only sample rate.

Verification Steps

Toggle a GPIO at ADC trigger and DMA interrupt for timing measurement.
Feed a known sine wave and verify sample spacing.
Switch between low and high input voltages to check channel settling.
Test worst-case firmware load and confirm no buffer overrun.
Log timestamps and sequence numbers for dropped samples.

Common Mistakes

Using maximum ADC clock rate while violating input acquisition time.
Scanning high-impedance and low-impedance channels with one sample time.
Starting conversions from a non-deterministic main loop.
Ignoring delta-sigma filter latency.
Doing heavy processing inside the ADC interrupt.

Summary

ADC throughput is not just the headline sample rate. Valid samples require enough acquisition time, conversion time, deterministic triggers, source settling, and buffering. Use timers and DMA for repeatable data streams, measure timing on hardware, and account for latency before using samples in control loops.

Mind Map

mindmap root((ADC Timing)) Terms Acquisition time Conversion time Throughput Latency Sample period Formulas Tsample equals Tacq plus Tconv fs equals 1 over Tsample Settling about N plus 1 ln2 RC SNR jitter uses 2 pi fin tj Design Timer trigger Per channel sample time DMA buffer Avoid long ISR Check delta sigma delay Verification GPIO timing Known waveform Step settling Buffer overrun test Common mistakes Too short acquisition Loop triggered samples Ignored latency ISR overload