ADC Timing and Throughput

ADC timing decides whether firmware receives valid samples at the right moments. A converter may advertise a maximum sample rate, but the useful throughput depends on acquisition time, conversion time, channel switching, filtering latency, interrupt overhead, DMA buffering, and the analog source settling fast enough.

Learning Objectives

By the end of this lesson, you should be able to:

• distinguish acquisition time, conversion time, throughput, and latency;
• estimate sample timing for multiplexed ADC channels;
• explain why source impedance affects acquisition;
• identify jitter and trigger timing problems;
• choose interrupt, polling, or DMA transfer strategies.

Timing Terms

For a simple SAR ADC sequence:

$$
T_\text{sample}=T_\text{acq}+T_\text{conv}+T_\text{overhead}
$$

$$
f_\text{sample}=\frac{1}{T_\text{sample}}
$$

Always distinguish sample rate per ADC from sample rate per channel. A 1 MS/s ADC scanning eight channels cannot deliver 1 MS/s on every channel unless there are eight ADC cores or a different sampling architecture.

Acquisition and Settling

A SAR ADC input often looks like a switch and small capacitor. When the sample switch closes, the external source must charge the capacitor to the input voltage. High source resistance needs more acquisition time.

A first-order settling estimate uses:

$$
V_\text{error}=V_\text{step}e^{-t/(RC)}
$$

For N-bit settling to within about 0.5 LSB, a common estimate is:

$$
t \ge (N+1)\ln(2)RC
$$

For 12-bit settling, that is about 9RC.

Worked example: if the effective source resistance is 10 kOhm and the sampling network behaves like 20 pF, then:

$$
RC=(10000)(20\times10^{-12})=200\ \text{ns}
$$

For 12-bit settling:

$$
t_\text{acq}\approx 9RC=1.8\ \mu s
$$

If firmware configures only 0.5 us acquisition time, the ADC may produce stable but wrong readings. Increasing sample time and watching whether the code changes is a quick settling diagnostic.

Multiplexed Channels

When one ADC scans many channels, total scan time matters:

$$
T_\text{scan}=\sum(T_\text{acq,ch}+T_\text{conv,ch})+T_\text{sequence overhead}
$$

A high-impedance temperature input may need a long sample time, while a buffered current input may allow a short sample time. Many MCUs let each channel use a different acquisition setting.

Worked Example: Scan Throughput

Suppose an ADC scans four channels:

Ignoring small sequence overhead:

$$
T_\text{scan}=(1+1)+(1+1)+(10+1)+(3+1)=19\ \mu s
$$

The scan rate is:

$$
f_\text{scan}=\frac{1}{19\ \mu s}=52.6\ \text{k scans/s}
$$

Each channel receives one sample per scan, so each channel is also 52.6 kS/s. If the same ADC instead interleaves extra current samples between slow channels, the per-channel rates must be calculated from the actual sequence, not from the headline ADC clock.

Triggering and Jitter

Timer-triggered ADC sampling gives more consistent timing than starting conversions from a busy main loop. Jitter is sample-time uncertainty. It matters most for high-frequency signals because timing error becomes amplitude error.

For a sine wave, jitter-limited SNR is approximately:

$$
\text{SNR}\text{jitter}=-20\log{10}(2\pi f_\text{in}t_j)
$$

where t_j is RMS jitter in seconds.

For f_in = 10 kHz and t_j = 100 ns:

$$
\text{SNR}\text{jitter}=-20\log{10}(2\pi(10000)(100\times10^{-9}))=44\ \text{dB}
$$

That is only about 7 effective bits for that signal, even if the ADC has more nominal resolution. Timer triggers, clean clocks, and predictable interrupt/DMA handling matter as signal frequency rises.

Interrupts, Polling, and DMA

DMA is usually the right choice for continuous multi-channel acquisition because it separates sample timing from firmware scheduling.

Use double buffering for streams. Firmware processes one half of the buffer while DMA fills the other half. The processing time must be shorter than the buffer-fill time:

$$
T_\text{process}<\frac{N_\text{buffer}/2}{f_\text{sample,total}}
$$

If this is not true, the system needs a larger buffer, lower sample rate, faster processing path, or hardware filtering.

Latency in Delta-Sigma ADCs

Delta-sigma ADCs include digital filters. The output data rate may be 1 kS/s, but a step input can take several output periods to settle depending on filter type. For control loops, check group delay and step response, not only sample rate.

Discard samples after changing gain, channel, reference, or filter settings when the datasheet requires it. The first reported value after a configuration change may still contain information from the previous input.

Verification Steps

1. Toggle a GPIO at ADC trigger and DMA interrupt for timing measurement.
2. Feed a known sine wave and verify sample spacing.
3. Switch between low and high input voltages to check channel settling.
4. Test worst-case firmware load and confirm no buffer overrun.
5. Log timestamps and sequence numbers for dropped samples.
6. Change the input from low to high immediately before a scanned channel and confirm the next channel is not contaminated.

Common Mistakes

• Using maximum ADC clock rate while violating input acquisition time.
• Scanning high-impedance and low-impedance channels with one sample time.
• Starting conversions from a non-deterministic main loop.
• Ignoring delta-sigma filter latency.
• Doing heavy processing inside the ADC interrupt.
• Confusing total sequencer throughput with per-channel sample rate.
• Trusting the first sample after a mux, gain, or reference change without checking settling.

Summary

ADC throughput is not just the headline sample rate. Valid samples require enough acquisition time, conversion time, deterministic triggers, source settling, and buffering. Use timers and DMA for repeatable data streams, measure timing on hardware, and account for latency before using samples in control loops.

Further Reading

• Microchip: ADC Acquisition Time
• Texas Instruments: SAR ADC Input Settling
• Analog Devices: Aperture Jitter and ADCs

Mind Map