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ADC Architectures

An analog-to-digital converter turns an input voltage into a digital code. Different ADC architectures make different tradeoffs among speed, resolution, latency, input drive, power, noise, and cost. Choosing an ADC starts by matching the architecture to the signal and system timing.

Learning Objectives

By the end of this lesson, you should be able to:

  • describe the operating idea of common ADC architectures;
  • compare SAR, delta-sigma, pipeline, flash, and integrating ADCs;
  • identify latency, throughput, and input-drive tradeoffs;
  • choose an ADC family for typical embedded measurements;
  • spot datasheet details that affect firmware and analog design.

ADC Selection Axes

The best ADC depends on more than bit count.

Requirement Why it matters
resolution smallest code step
accuracy closeness to true value after errors
throughput samples per second available to firmware
latency delay from input event to output code
input bandwidth how fast the analog input may change
input drive source impedance and settling requirement
power battery and thermal budget
interface MCU pin count and timing

SAR ADC

A successive-approximation-register ADC compares the input against a binary search generated by an internal DAC. SAR ADCs are common inside microcontrollers.

flowchart LR VIN["Input sample"] --> SH["Sample and hold"] SH --> CMP["Comparator"] SAR["SAR logic"] --> DAC["Internal DAC"] DAC --> CMP CMP --> SAR SAR --> CODE["Digital code"]

Strengths:

  • good resolution from 8 to 18 bits;
  • low latency;
  • moderate to high speed;
  • easy multiplexing for many channels.

Watch out for input sampling capacitor settling. High source impedance or too-short acquisition time causes wrong codes.

Delta-Sigma ADC

A delta-sigma ADC oversamples the input, shapes quantization noise, and digitally filters the result. It is excellent for precision low-bandwidth measurements.

Strengths:

  • high resolution and noise performance;
  • strong rejection of selected interference such as 50/60 Hz;
  • good for weigh scales, temperature, pressure, and energy metering.

Watch out for digital filter latency and lower output data rate. A step change may take multiple conversion periods to settle.

Pipeline ADC

A pipeline ADC converts in stages. Each stage resolves some bits and passes a residue to the next stage.

Strengths:

  • high sample rates;
  • useful for communications, imaging, radar, and high-speed instrumentation.

Watch out for latency, power, clock quality, layout, and interface bandwidth.

Flash ADC

A flash ADC uses many comparators in parallel. It is extremely fast but grows rapidly in comparator count.

For N bits, an ideal flash ADC needs:

$$
2^N-1\ \text{comparators}
$$

An 8-bit flash ADC needs 255 comparators, which explains why flash converters are fast but area- and power-hungry.

Integrating and Dual-Slope ADC

Integrating ADCs measure by charging and discharging an integrator over controlled time intervals. Dual-slope ADCs are common in digital multimeters.

Strengths:

  • excellent noise rejection over integration window;
  • stable readings for slow signals;
  • good line-frequency rejection.

Watch out for slow update rate. They are not suitable for fast control loops.

Architecture Comparison

Architecture Typical strength Typical limitation Common use
SAR balanced speed and latency input settling MCU ADC, control loops
delta-sigma high resolution latency, bandwidth weigh scale, metering
pipeline high speed power, latency communications
flash fastest conversion comparator count very high speed capture
dual-slope noise rejection slow multimeters

Firmware Consequences

ADC architecture affects firmware design. SAR ADCs need channel acquisition timing and often DMA. Delta-sigma ADCs need data-ready handling and filter-settling awareness. High-speed converters need deterministic buffering and interfaces such as SPI, parallel buses, JESD204, or LVDS.

Common Mistakes

  • Choosing the highest bit count without checking noise-free resolution.
  • Using a delta-sigma ADC in a fast control loop without accounting for latency.
  • Driving a SAR ADC directly from a large resistor divider.
  • Ignoring reference requirements and layout.
  • Assuming MCU ADC performance matches external precision ADCs.

Summary

SAR ADCs are the embedded default for multiplexed control and measurement. Delta-sigma ADCs are strong for high-resolution low-bandwidth signals. Pipeline and flash ADCs serve high-speed applications, while integrating ADCs serve slow accurate instruments. Architecture choice determines analog front-end design, firmware timing, latency, filtering, and achievable accuracy.

Further Reading

Mind Map

mindmap root((ADC Architectures)) SAR Binary search Sample hold Low latency MCU common Needs input settling Delta sigma Oversampling Noise shaping Digital filter High resolution Has latency High speed Pipeline stages Flash comparators Clock quality Interface bandwidth Integrating Dual slope Slow stable readings Line noise rejection Multimeters Selection Resolution Throughput Latency Source impedance Power Common mistakes Bits over accuracy Ignoring latency Weak ADC driver Poor reference layout