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ADC Architectures

An analog-to-digital converter turns an input voltage into a digital code. Different ADC architectures make different tradeoffs among speed, resolution, latency, input drive, power, noise, and cost. Choosing an ADC starts by matching the architecture to the signal and system timing.

Learning Objectives

By the end of this lesson, you should be able to:

  • describe the operating idea of common ADC architectures;
  • compare SAR, delta-sigma, pipeline, flash, and integrating ADCs;
  • identify latency, throughput, and input-drive tradeoffs;
  • choose an ADC family for typical embedded measurements;
  • spot datasheet details that affect firmware and analog design.

ADC Selection Axes

The best ADC depends on more than bit count.

Requirement Why it matters
resolution smallest code step
accuracy closeness to true value after errors
throughput samples per second available to firmware
latency delay from input event to output code
input bandwidth how fast the analog input may change
input drive source impedance and settling requirement
power battery and thermal budget
interface MCU pin count and timing

Start from the signal, not the catalog headline. A thermistor, a current-control loop, an audio stream, a motor vibration sensor, and an oscilloscope front end all convert voltage to codes, but they need different latency, bandwidth, noise, and firmware behavior.

SAR ADC

A successive-approximation-register ADC compares the input against a binary search generated by an internal DAC. SAR ADCs are common inside microcontrollers.

flowchart LR VIN["Input sample"] --> SH["Sample and hold"] SH --> CMP["Comparator"] SAR["SAR logic"] --> DAC["Internal DAC"] DAC --> CMP CMP --> SAR SAR --> CODE["Digital code"]

Strengths:

  • good resolution from 8 to 18 bits;
  • low latency;
  • moderate to high speed;
  • easy multiplexing for many channels.

Watch out for input sampling capacitor settling. High source impedance or too-short acquisition time causes wrong codes.

For many SAR inputs, the external source must settle within about 0.5 LSB during acquisition:

$$
t_\text{acq}\ge (N+1)\ln(2)R_\text{source}C_\text{sample}
$$

The datasheet may provide a more exact equation or a maximum recommended source impedance. Follow that value before trusting the ideal estimate.

Delta-Sigma ADC

A delta-sigma ADC oversamples the input, shapes quantization noise, and digitally filters the result. It is excellent for precision low-bandwidth measurements.

Strengths:

  • high resolution and noise performance;
  • strong rejection of selected interference such as 50/60 Hz;
  • good for weigh scales, temperature, pressure, and energy metering.

Watch out for digital filter latency and lower output data rate. A step change may take multiple conversion periods to settle.

flowchart LR VIN["Input"] --> MOD["1-bit or multi-bit modulator"] MOD --> FILT["Digital decimation filter"] FILT --> CODE["High-resolution output code"] CLK["Oversampling clock"] --> MOD

Delta-sigma output rate is not the same as modulator clock rate. The digital filter trades bandwidth for noise performance. Some filters provide strong 50/60 Hz rejection only at specific output data rates.

Pipeline ADC

A pipeline ADC converts in stages. Each stage resolves some bits and passes a residue to the next stage.

Strengths:

  • high sample rates;
  • useful for communications, imaging, radar, and high-speed instrumentation.

Watch out for latency, power, clock quality, layout, and interface bandwidth.

Pipeline converters can deliver many samples per second, but the output code may correspond to an input several clock cycles earlier. That latency is acceptable in capture systems but can be difficult in fast feedback loops.

Flash ADC

A flash ADC uses many comparators in parallel. It is extremely fast but grows rapidly in comparator count.

For N bits, an ideal flash ADC needs:

$$
2^N-1\ \text{comparators}
$$

An 8-bit flash ADC needs 255 comparators, which explains why flash converters are fast but area- and power-hungry.

Because every threshold must be accurate, flash ADCs are usually used at modest resolution. Very high-speed converters often combine flash sub-ADCs inside pipeline or folding architectures.

Integrating and Dual-Slope ADC

Integrating ADCs measure by charging and discharging an integrator over controlled time intervals. Dual-slope ADCs are common in digital multimeters.

Strengths:

  • excellent noise rejection over integration window;
  • stable readings for slow signals;
  • good line-frequency rejection.

Watch out for slow update rate. They are not suitable for fast control loops.

The core advantage is that the measurement averages over a controlled time window. If the integration time is chosen as one full mains period, line-frequency noise is strongly rejected.

Architecture Comparison

Architecture Typical strength Typical limitation Common use
SAR balanced speed and latency input settling MCU ADC, control loops
delta-sigma high resolution latency, bandwidth weigh scale, metering
pipeline high speed power, latency communications
flash fastest conversion comparator count very high speed capture
dual-slope noise rejection slow multimeters

Worked Selection Examples

Application Good architecture Why
MCU battery monitor SAR low latency, simple multiplexing, enough resolution
load cell or weigh scale delta-sigma high resolution, low bandwidth, line-noise rejection
motor phase current loop SAR deterministic timing and low latency
oscilloscope front end pipeline or flash-assisted high input bandwidth and sample rate
handheld multimeter dual-slope or integrating stable slow readings and noise rejection

If the signal is slow but precision is high, compare delta-sigma noise and filter latency. If the signal is fast and used for control, latency and deterministic trigger behavior usually matter more than headline resolution.

Firmware Consequences

ADC architecture affects firmware design. SAR ADCs need channel acquisition timing and often DMA. Delta-sigma ADCs need data-ready handling and filter-settling awareness. High-speed converters need deterministic buffering and interfaces such as SPI, parallel buses, JESD204, or LVDS.

Check these firmware-facing details before freezing hardware:

  • whether conversion results arrive immediately, after a pipeline delay, or after a digital-filter delay;
  • whether channel changes invalidate one or more first samples;
  • whether the data-ready pin, SPI frame, or DMA transfer can meet the required timing;
  • whether calibration registers, reference startup, or filter settling must be sequenced at boot;
  • whether raw binary, offset-binary, or two's-complement output format is used.

Common Mistakes

  • Choosing the highest bit count without checking noise-free resolution.
  • Using a delta-sigma ADC in a fast control loop without accounting for latency.
  • Driving a SAR ADC directly from a large resistor divider.
  • Ignoring reference requirements and layout.
  • Assuming MCU ADC performance matches external precision ADCs.
  • Multiplexing delta-sigma channels without allowing filter settling after each channel change.
  • Forgetting that high-speed ADCs need clock, layout, and data-interface design as much as converter selection.

Summary

SAR ADCs are the embedded default for multiplexed control and measurement. Delta-sigma ADCs are strong for high-resolution low-bandwidth signals. Pipeline and flash ADCs serve high-speed applications, while integrating ADCs serve slow accurate instruments. Architecture choice determines analog front-end design, firmware timing, latency, filtering, and achievable accuracy.

Further Reading

Mind Map

mindmap root((ADC Architectures)) SAR Binary search Sample hold Low latency MCU common Needs input settling Tacq set by source R and Csample Delta sigma Oversampling Noise shaping Digital filter High resolution Has latency ODR not mod clock Line noise rejection High speed Pipeline stages Flash comparators Flash uses 2 power N minus 1 comparators Clock quality Interface bandwidth Pipeline delay Integrating Dual slope Slow stable readings Line noise rejection Multimeters Selection Resolution Throughput Latency Source impedance Power Output format Practical checks Data ready timing First sample after mux Reference startup DMA bandwidth Common mistakes Bits over accuracy Ignoring latency Weak ADC driver Poor reference layout