I²S — Inter-IC Sound Protocol

I²S is a synchronous serial bus made for digital audio between chips. Microcontrollers, audio codecs, DACs, ADCs, MEMS microphones, and digital amplifiers use it to move raw PCM samples with precise timing and low framing overhead.

Learning Objectives

By the end of this lesson, you should be able to:

• identify the BCLK, WS/LRCLK, SD, and optional MCLK signals;
• calculate bit-clock frequency from sample rate, channels, and slot width;
• explain standard I²S timing and how it differs from left-justified audio;
• choose master/slave clock roles for an audio link;
• debug channel swap, bit-depth, clock, and DMA problems.

Why Audio Needs Its Own Bus

UART, SPI, and I²C can move bytes, but audio is a continuous timed stream:

• samples must arrive at a fixed sample rate such as 44.1 kHz or 48 kHz;
• left and right channel boundaries must be unambiguous;
• sample bits must be aligned the same way at the transmitter and receiver;
• the transfer must not pause randomly while audio is playing.

I²S solves this with a clocked stream and a word-select signal.

The Signals

The I²S master generates clocks. The data source can be either side: an MCU sends audio to a DAC, while a digital microphone sends audio back to the MCU.

Standard I²S Timing

In standard I²S, the word-select transition occurs one bit clock before the most significant bit of the next sample. This gives the receiver one clock edge to prepare for the next channel.

title "Standard I2S frame idea"
time start=0 end=16 unit=bit divisions=16

BCLK: square label="BCLK" low=0 high=1 duty=50 cycles=8 unit=logic color=#2563eb
WS: square label="WS left then right" low=0 high=1 duty=50 cycles=1 unit=logic color=#16a34a
SD: square label="SD sample bits MSB first" low=0 high=1 duty=50 cycles=3 phase=45 unit=logic color=#dc2626

marker L at=1 label="left MSB"
marker R at=9 label="right MSB"

This waveform is explanatory. It does not represent a specific audio value or analog output.

Bit-Clock Calculations

The bit clock depends on sample rate, number of channels, and bits per slot.

BCLK = sample_rate * channels * slot_width

Worked examples:

Many systems carry 24-bit samples in 32-bit slots, so do not assume sample depth and slot width are the same.

Word Select and Channel Meaning

In common standard I²S:

• WS = 0 usually means left channel;
• WS = 1 usually means right channel;
• data is sent most-significant bit first;
• unused least-significant slot bits are padded.

Always verify the datasheet. Some devices support standard I²S, left-justified, right-justified, DSP mode, and TDM mode through configuration registers.

Master Clock

Some audio codecs need MCLK, often a multiple of the sample rate:

MCLK = 256 * Fs, 384 * Fs, or 512 * Fs

For 48 kHz audio, 256 * Fs = 12.288 MHz. For 44.1 kHz audio, 256 * Fs = 11.2896 MHz. Mixing 44.1 kHz-family and 48 kHz-family clocks carelessly causes drift, clicks, or resampling artifacts.

DMA and Buffers

Audio is continuous, so firmware usually uses DMA:

The CPU should refill one half of a buffer while DMA plays the other half. If the CPU misses the deadline, the output repeats stale data or underflows, producing clicks.

I²S Variants

Both endpoints must use the same format, slot width, sample rate, and channel order.

Practical Checks

• Confirm the audio chip is configured for the same format as the MCU peripheral.
• Verify BCLK = Fs * channels * slot_width.
• Check whether the codec needs MCLK.
• Use DMA or FIFO interrupts rather than blocking byte writes.
• Keep audio clocks low-jitter when quality matters.
• Probe WS to confirm the sample rate directly.
• If left and right are swapped, check WS polarity and data-buffer order.

Common Mistakes

• Treating I²S like SPI and pausing the clock mid-stream.
• Confusing 24-bit samples with 24-bit slots when the device expects 32-bit slots.
• Using a 48 kHz clock tree with 44.1 kHz audio files without resampling.
• Setting standard I²S on one device and left-justified on the other.
• Forgetting that many codecs are configured over a separate I²C or SPI control bus.
• Refilling DMA buffers too late and creating audio clicks.

Summary

I²S is a clocked PCM audio stream with separate bit-clock, word-select, and serial-data signals. Correct operation depends on matching format, sample rate, slot width, channel order, master-clock requirements, and DMA timing. It carries audio samples only; codec configuration usually happens over a separate control interface.

Further Reading

• NXP, I²S bus specification.
• Texas Instruments, audio serial interface application notes.
• STMicroelectronics, SAI and I²S peripheral application notes.
• Espressif, ESP32 I²S driver documentation.

Mind Map