I²S — Inter-IC Sound Protocol

I²S (Inter-IC Sound, pronounced "I-squared-S" or "I-two-S") is a synchronous serial protocol invented by Philips in 1986 specifically for carrying digital audio data between chips. If you have ever connected a DAC, a digital microphone (MEMS mic), or an audio codec to a microcontroller, you have used I²S.

Why a Separate Protocol for Audio?

SPI and UART can carry bytes. But audio has special requirements:

Stereo: two channels (Left and Right) must be perfectly synchronised
Sample rate locked to clock: audio must arrive at exactly 44.1 kHz or 48 kHz — no jitter
No framing overhead: raw PCM samples, no start/stop bits, no addresses
Continuous stream: audio never stops mid-transfer the way a SPI transaction does

I²S solves all of these with a dedicated three-wire interface.

The Three Wires

flowchart LR classDef mcu fill:#dbeafe,stroke:#2563eb,color:#1e3a5f classDef wire fill:#dcfce7,stroke:#16a34a,color:#14532d classDef dev fill:#fee2e2,stroke:#dc2626,color:#7f1d1d MCU["Microcontroller\n(I²S Master)"]:::mcu DAC["Audio DAC\nor\nDigital Mic\n(I²S Slave)"]:::dev MCU -->|"SCK — Bit Clock\n(shifts each audio bit)"| DAC MCU -->|"WS — Word Select\n(Left=LOW, Right=HIGH)"| DAC MCU <-->|"SD — Serial Data\n(PCM audio samples)"| DAC

Pin	Name	Direction	Purpose
SCK	Serial Clock (Bit Clock, BCLK)	Master → Slave	Clocks each individual audio bit
WS	Word Select (LR Clock, LRCLK)	Master → Slave	LOW = Left channel, HIGH = Right channel
SD	Serial Data	Either direction	PCM audio samples, MSB first

Optional 4th pin: MCLK (Master Clock) — some audio codecs need a higher-speed reference clock (typically 256 × sample rate). Not always required.

How Audio Samples Are Framed

I²S carries raw PCM (Pulse Code Modulation) samples — the same binary representation used in WAV files. The WS line defines the channel boundary:

SCK:  _‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_‾_
WS:   ___________________________‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
SD:       [  LEFT channel sample, MSB first  ] [ RIGHT channel  ]
           b15 b14 b13 ...              b0       b15 b14 ...  b0

WS transitions one clock before the MSB of the new channel
Each half-period of WS = one complete sample (Left or Right)
Sample depth is flexible: 16-bit, 24-bit, or 32-bit are all common

At 44.1 kHz stereo 16-bit: SCK = 44100 × 2 × 16 = 1.41 MHz
At 48 kHz stereo 32-bit: SCK = 48000 × 2 × 32 = 3.07 MHz

Master vs Slave — Who Generates the Clocks?

sequenceDiagram participant MCU as MCU (I²S Master) participant DAC as DAC Chip (Slave) Note over MCU,DAC: MCU generates SCK and WS at the exact sample rate MCU->>DAC: SCK starts — bits clock out continuously MCU->>DAC: WS = LOW — Left channel sample follows MCU->>DAC: SD: 1000000000000000 (Left sample = 0x8000) MCU->>DAC: WS = HIGH — Right channel follows MCU->>DAC: SD: 0111111111111111 (Right sample = 0x7FFF) Note over MCU,DAC: This repeats at 44,100 or 48,000 times per second

The I²S master (usually the microcontroller) generates SCK and WS. The slave (DAC, ADC, or microphone) just follows the clocks.

Some audio codecs can also operate as master — useful when the codec has a more accurate crystal for the audio sample rate.

I²S vs SPI — Why Not Just Use SPI?

	SPI	I²S
Clocking	Master controls, can pause	Continuous — must not pause
Channels	Single data stream	Left/Right defined by WS line
Use case	Byte-by-byte transfers	Streaming PCM audio
Sample alignment	No concept	Strict: WS must align to sample boundaries
Common for	Flash, sensors, displays	DAC, ADC, MEMS mic, codecs

SPI can technically carry audio bytes, but you lose channel synchronisation and timing guarantees. Audio chips expect I²S.

Common I²S Devices

Device Type	Examples	Notes
Audio DAC	PCM5102A, UDA1334, MAX98357	Converts I²S to analog output
Audio ADC	PCM1808, CS5343	Converts analog mic to I²S
MEMS Microphone	INMP441, SPH0645	Digital mic with I²S output
Audio Codec	WM8960, ES8388	Combined DAC+ADC, often I²C configurable
I²S Amplifier	MAX98357A	Receives I²S, outputs speaker power directly

I²S on Microcontrollers

Most modern microcontrollers have dedicated I²S peripherals:

Platform	I²S Support
ESP32	2× I²S peripherals, DMA-driven
STM32	SAI (Serial Audio Interface), compatible with I²S
RP2040 (Pi Pico)	PIO-based I²S (any pins)
nRF52840	I²S peripheral with MCLK output
Arduino (basic)	No hardware I²S — software only, too slow

I²S Variants You Will See

Variant	Description
Standard I²S (Philips)	WS goes low one SCK before MSB — the original Philips spec
Left-justified	WS transitions and MSB start simultaneously
Right-justified (Sony)	MSB is at the end of the WS period
TDM (Time Division Multiplex)	Multiple channels on one SD line, WS has multiple slots

Most chips support all three main modes via a register setting. When connecting chips, make sure both sides use the same format.

Key Takeaway

I²S is a streaming audio bus — three wires carry continuous, perfectly synchronised, stereo PCM audio at a precise sample rate. The WS line tells you which channel every sample belongs to; the SCK clocks each bit; the SD wire carries the raw audio data.

It is a hardware protocol — I²S defines the electrical timing and framing of audio bits. It says nothing about what songs to play, what volume to set, or how to configure the DAC. Those are handled by higher-level software and usually by a separate I²C control bus to the same chip.